Enhancing data cache reliability by the addition of a small fully-associative replication cache

ABSTRACT

Soft error conscious cache design is a necessity for reliable computing. ECC or parity-based integrity checking technique in use today either compromises performance for reliability or vice versa, and the N modular redundancy (NMR) scheme is too costly for microprocessors and applications with stringent cost constraint. This paper proposes a novel and cost-effective solution to enhance data reliability with minimum impact on performance. The idea is to add a small fully-associative cache to store the replica(s) of every write to the L1 data cache. The replicas can be used to detect and correct soft errors. The replication cache can also be used to increase performance by reducing the L1 data cache miss rate. Our experiments show that more than 97% read hits of the L1 data cache can find replicas available in a replication cache of 8 blocks.

REFERENCES

• 1: Johan Karlsson , Peter Liden , Peter Dahlgren , Rolf Johansson , Ulf Gunneflo, Using Heavy-Ion Radiation to Validate Fault-Handling Mechanisms, IEEE Micro, v.14 n.1, p.8-11, 13-23, February 1994 [doi>10.1109/40.259894 ]
• 2: Janusz Sosnowski, Transient Fault Tolerance in Digital Systems, IEEE Micro, v.14 n.1, p.24-35, February 1994 [doi>10.1109/40.259897 ]
• 3: Seongwoo Kim , Arun K. Somani, Area efficient architectures for information integrity in cache memories, Proceedings of the 26th annual international symposium on Computer architecture, p.246-255, May 01-04, 1999, Atlanta, Georgia, United States
• 4: Premkishore Shivakumar , Michael Kistler , Stephen W. Keckler , Doug Burger , Lorenzo Alvisi, Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic, Proceedings of the 2002 International Conference on Dependable Systems and Networks, p.389-398, June 23-26, 2002
• 5: Joydeep Ray , James C. Hoe , Babak Falsafi, Dual use of superscalar datapath for transient-fault detection and recovery, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
• 6: P. Sweazey. SRAM organization, control, and speed, and their effect on cache memory design. Midcon/87, pages 434--437, Septembe, 1987.
• 7: Hideki Imai, Essentials of Error-Control Coding Techniques, Academic Press, Inc., Orlando, FL, 1990
• 8: C. L. Chen and M. Y Hsiao. Error-correcting codes for semiconductor memory applications: a state of the art review. In Reliable Computer Systems - Design and Evaluation, pages 771--786, Digital Press, 2nd edition, 1992.
• 9: W. Zhang, S. Gurumurthi, M. kandemir and A. Sivasubramaniam. ICR: in-cache replication for enhancing data cache reliability. Proceedings of DSN, 2003.
• 10: Mitsuru Hamada , Eiji Fujiwara, A Class of Error Control Codes for Byte Organized Memory Systems -SbEC-(Sb+S)ED Codes-, IEEE Transactions on Computers, v.46 n.1, p.105-109, January 1997 [doi>10.1109/12.559809 ]
• 11: S. Park and B. Bose. Burst asymmetric/unidirectional error correcting/detecting codes. Proceeding of International Symposium on Fault-Tolerant Computing, pages 273--280, June 1990.
• 12: Eric Rotenberg, AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors, Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, p.84, June 15-18, 1999
• 13: Steven K. Reinhardt , Shubhendu S. Mukherjee, Transient fault detection via simultaneous multithreading, Proceedings of the 27th annual international symposium on Computer architecture, p.25-36, June 2000, Vancouver, British Columbia, Canada
• 14: Todd M. Austin, DIVA: a reliable substrate for deep submicron microarchitecture design, Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture, p.196-207, November 16-18, 1999, Haifa, Israel
• 15: V. Degalahal , N. Vijaykrishnan , M. J. Irwin, Analyzing Soft Errors in Leakage Optimized SRAM Design, Proceedings of the 16th International Conference on VLSI Design, p.227, January 04-08, 2003
• 16: Understanding Soft and Firm Errors in Semiconductor Devices. Actel Whitepaper, 2002.
• 17: Alan Jay Smith, Cache Memories, ACM Computing Surveys (CSUR), v.14 n.3, p.473-530, Sept. 1982 [doi>10.1145/356887.356892]
• 18: John L. Hennessy , David A. Patterson, Computer architecture (2nd ed.): a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1996
• 19: Norman P. Jouppi, Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers, Proceedings of the 17th annual international symposium on Computer Architecture, p.364-373, May 28-31, 1990, Seattle, Washington, United States
• 20: http://www.simplescalar.com.
• 21: http://www.spec.org.
• 22: AMD Athlon 64 FX Processor Data Sheet.
• 23: P. Shivakumar and N. Jouppi. CACTI 3.0: An integrated cache timing, power and area model. WRL Research Report 2001.
• 24: Johnson Kin , Munish Gupta , William H. Mangione-Smith, The filter cache: an energy efficient memory structure, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.184-193, December 01-03, 1997, Research Triangle Park, North Carolina, United States

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Cache memories

General Terms:
Design, Performance, Reliability

Keywords:
in-cache replication, soft error, write-back cache