Article

Microarchitectural techniques for power gating of execution units

Authors:

Alper Buyuktosunoglu,

Viji Srinivasan,

Pradip BoseAuthors Info & Claims

ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design

Pages 32 - 37

https://doi.org/10.1145/1013235.1013249

Published: 09 August 2004 Publication History

Abstract

Leakage power is a major concern in current and future microprocessor designs. In this paper, we explore the potential of architectural techniques to reduce leakage through power-gating of execution units. This paper first develops parameterized analytical equations that estimate the break-even point for application of power-gating techniques. The potential for power gating execution units is then evaluated, for the range of relevant break-even points determined by the analytical equations, using a state-of-the-art out-of-order superscalar processor model. The power gating potential of the floating-point and fixed-point units of this processor is then evaluated using three different techniques to detect opportunities for entering sleep mode; ideal, time-based, and branch-misprediction-guided. Our results show that using the time-based approach, floating-point units can be put to sleep for up to 28% of the execution cycles at a performance loss of 2%. For the more difficult to power-gate fixed-point units, the branch misprediction guided technique allows the fixed-point units to be put to sleep for up to 40% more of the execution cycles compared to the simpler time-based technique, with similar performance impact. Overall, our experiments demonstrate that architectural techniques can be used effectively in power-gating execution units.

References

[1]

Borkar, S. Design Challenges of Technology Scaling. IEEE Micro 19, 4 (1999).

Digital Library

[2]

Clark, L., Demmons, S., Deutscher, N., and Ricci, F. Standby Power Management for a 0.18um Microprocessor. In ISLPED (2002).

Digital Library

[3]

Dropsho, S., Kursun, V., Albonesi, D. H., Dwarkadas, S., and Friedman, E. G. Managing Static Leakage Energy in Microprocessor Functional Units. In MICRO (2002).

Digital Library

[4]

Duarte, D., Tsai, Y. F., Vijaykrishnan, N., and Irwin, M. J. Evaluating Run-Time Techniques for Leakage Power Reduction. In ASPDAC (2002).

Digital Library

[5]

Flautner, K., Kim, N. S., Martin, S., Blaauw, D., and Mudge, T. Drowsy Caches: Simple Techniques for Reducing Leakage Power. In ISCA (2002).

Digital Library

[6]

Hamzaoglu, F., and Stan, M. R. Circuit-Level Techniques to Control Gate Leakage for sub-100nm CMOS. In ISLPED (2002).

Digital Library

[7]

Heo, S., Barr, K., Hampton, M., and Asanovic, K. Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines. In ISCA (137-147, 2002).

Digital Library

[8]

Iyengar, V., Trevillyan, L. H., and Bose, P. Representative Traces for Processor Models with Infinite Cache. In HPCA (1996).

Digital Library

[9]

Johnson, M., Somasekhar, D., Chiou, L., and Roy, K. Leakage Control With Efficient Use of Transistor Stacks in Single Threshold CMOS . IEEE Transactions on VLSI Systems 10 (2002).

Digital Library

[10]

Kao, J., and Chandrakasan, A. Dual-Threshold Voltage Techniques for Low-Power Digital Circuits. IEEE Journal of Solid State Circuits 35 (2000).

[11]

Kaxiras, S., Hu, Z., and Martonosi, M. Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power. In ISCA (2001).

Digital Library

[12]

Moudgill, M., Bose, P., and Moreno, J. H. Validation of Turandot, a Fast Processor Model for Microarchitecture Exploration. In IPCCC (1999).

[13]

Moudgill, M., Wellman, J. D., and Moreno, J. H. Environment for PowerPC Microarchitecture Exploration. IEEE Micro 19, 3 (1999).

Digital Library

[14]

Powell, M., Yang, S., Falsafi, B., Roy, K., and Vijaykumar, T. Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories. In ISLPED (2000).

Digital Library

[15]

Rele, S., Pande, S., Onder, S., and Gupta, R. Optimizing Static Power Dissipation by Functional Units in Superscalar Processors. In Int'l Conf. on Compiler Construction (2002).

Digital Library

[16]

Tendler, J. M., Dodson, J. S., Fields, J. S., Le, H., and Sinharoy, B. POWER4 System Microarchitecture. IBM Journal Research and Development 46, 1 (2002).

Digital Library

Cited By

Ouyang YChen ZXu DLiang H(2024)SPONGE+: A NoC-based power gating scheme for overall router column opening and closing controlMicroelectronics Journal10.1016/j.mejo.2024.106234149(106234)Online publication date: Jul-2024
https://doi.org/10.1016/j.mejo.2024.106234
Ouyang YCao CXu DZhou WHuang ZLiang H(2024)DBU-PG: energy-efficient noc design using dual-buffering power gatingThe Journal of Supercomputing10.1007/s11227-024-06000-480:10(13632-13656)Online publication date: 1-Jul-2024
https://dl.acm.org/doi/10.1007/s11227-024-06000-4
Trivedi AKung JKo J(2024)Architectures for Self-Powered Edge IntelligenceHandbook of Computer Architecture10.1007/978-981-97-9314-3_9(89-125)Online publication date: 21-Dec-2024
https://doi.org/10.1007/978-981-97-9314-3_9
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Index Terms

Microarchitectural techniques for power gating of execution units
1. Computer systems organization
  1. Architectures
    1. Serial architectures
      1. Pipeline computing

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Published In

cover image ACM Conferences

ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design

August 2004

414 pages

ISBN:1581139292

DOI:10.1145/1013235

General Chairs:
Rajiv Joshi
IBM
,
Kiyoung Choi
Seoul National University
,
Program Chairs:
Vivek Tiwari
Intel Corporation
,
Kaushik Roy
Purdue University

Copyright © 2004 ACM.

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Published: 09 August 2004

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ISLPED04

Sponsor:

ISLPED04: International Symposium on Low Power Electronics and Design

August 9 - 11, 2004

California, Newport Beach, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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https://doi.org/10.1016/j.mejo.2024.106234
Ouyang YCao CXu DZhou WHuang ZLiang H(2024)DBU-PG: energy-efficient noc design using dual-buffering power gatingThe Journal of Supercomputing10.1007/s11227-024-06000-480:10(13632-13656)Online publication date: 1-Jul-2024
https://dl.acm.org/doi/10.1007/s11227-024-06000-4
Trivedi AKung JKo J(2024)Architectures for Self-Powered Edge IntelligenceHandbook of Computer Architecture10.1007/978-981-97-9314-3_9(89-125)Online publication date: 21-Dec-2024
https://doi.org/10.1007/978-981-97-9314-3_9
Zoni DGalimberti AFornaciari W(2023)A Survey on Run-time Power Monitors at the EdgeACM Computing Surveys10.1145/359304455:14s(1-33)Online publication date: 18-Apr-2023
https://dl.acm.org/doi/10.1145/3593044
Zhou WOuyang YXu DHuang ZLiang HWen X(2023)Energy-Efficient Multiple Network-on-Chip Architecture With Bandwidth ExpansionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.324485931:4(442-455)Online publication date: Apr-2023
https://doi.org/10.1109/TVLSI.2023.3244859
Si QChowdhury PSreekumar RSchafer B(2023)Application Specific Approximate Behavioral ProcessorIEEE Transactions on Sustainable Computing10.1109/TSUSC.2022.32221178:2(165-179)Online publication date: 1-Apr-2023
https://doi.org/10.1109/TSUSC.2022.3222117
Hafezan MAtoofian E(2023)Mixed-Precision Architecture for GPU Tensor Cores2023 IEEE Smart World Congress (SWC)10.1109/SWC57546.2023.10448789(1-8)Online publication date: 28-Aug-2023
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Wu MYan MYang XLi WZhang ZYe XFan D(2023)Characterizing and Understanding Defense Methods for GNNs on GPUsIEEE Computer Architecture Letters10.1109/LCA.2023.330463822:2(137-140)Online publication date: Jul-2023
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Krishnamoorthy RKrishnan KChokkalingam B(2023)Integrated analysis of power and performance for cutting edge Internet of Things microprocessor architecturesMicroprocessors and Microsystems10.1016/j.micpro.2023.10481598(104815)Online publication date: Apr-2023
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Atoofian E(2023)PTTS: Power-aware tensor cores using two-sided sparsityJournal of Parallel and Distributed Computing10.1016/j.jpdc.2022.11.004173(70-82)Online publication date: Mar-2023
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