Delayed line bus scheme

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses

Full text

Pdf (185 KB)

Source

International Symposium on Low Power Electronics and Design archive
Proceedings of the 2004 international symposium on Low power electronics and design table of contents

Newport Beach, California, USA

POSTER SESSION: Cache and bus design table of contents

Pages: 66 - 69

Year of Publication: 2004

ISBN:1-58113-929-2

Authors

Maged Ghoneima	Northwestern University, Evanston, IL
Yehea Ismail	Northwestern University, Evanston, IL

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 14, Citation Count: 1

Additional Information:

abstract references cited by index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTex EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/1013235.1013257 What is a DOI?

ABSTRACT

This paper presents a comprehensive qualitative and analytical analysis of the effect of relative delay on the dissipated energy of coupled lines. Closed form expressions modeling the effect of relative delay on the dissipated energy, and the Miller coupling factor, MCF, are also presented. Skewing the worst switching case is shown to provide up to 50% reduction in energy dissipation. This observation was implemented in a low-power bus scheme, DLBS, which leads to a power reduction of up to 25%.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Paul P. Sotiriadis , Anantha P. Chandrakasan, A bus energy model for deep submicron technology, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.341-350, June 2002 [doi>10.1109/TVLSI.2002.1043337 ]
	2	R. Kumar, "Interconnect and Noise Immunity Design for the Pentium® 4 Processor," Intel Tech. Journal, Q1, 2001.
	3	Youngsoo Shin , Takayasu Sakurai, Coupling-driven bus design for low-power application-specific systems, Proceedings of the 38th conference on Design automation, p.750-753, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379059]
	4	Mircea R. Stan , Wayne P. Burleson, Bus-invert coding for low-power I/O, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.1, p.49-58, March 1995 [doi>10.1109/92.365453 ]
	5	Kei Hirose , Hiroto Yasuura, A bus delay reduction technique considering crosstalk, Proceedings of the conference on Design, automation and test in Europe, p.441-445, March 27-30, 2000, Paris, France [doi>10.1145/343647.343815]