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A mixed-mode extraction flow for high performance microprocessors

Published: 27 January 2004 Publication History

Abstract

This paper describes a mixed mode chip level extraction flow deployed in high performance microprocessor designs. Two extractors of different accuracy levels are integrated to achieve best trade-off between run-time and precision. The goal is to provide sufficient accuracy at different design stages and achieve minimum extraction time possible. Three different extraction modes are made available through combination of an in-house 2D extractor and a vendor 3D extractor: 2D estimated, 2D actual and 3D extraction. The applications in real design projects showed around 75% extraction time-savings by combining these three modes together with a guarantee on meeting timing closure at the end.

References

[1]
Gary, S., Ippolito, P., Gerosa, G., Dietz, C., Eno, J. and Sanchez, H., "PowerPC 603, a microprocessor for portable computers," Design & Test of Computers, IEEE, vol. 11, no. 4, pp. 14--23, 1994.
[2]
2002 International Technology Roadmap for Semiconductor, available by WWW at "http://public.itrs.net/Files/2002Update/Home.pdf."
[3]
Synopsys Products: Star-RCXT Datasheet, available by WWW at: "http://www.synopsys.com/products/avmrg/star_rcxt_ds.html."
[4]
Odabasioglu, A., Celik, M., Pileggi, L. T., "PRIMA: passive reduced-order interconnect macromodeling algorithm,", IEEE Trans. CAD. vol. 17, no. 8, pp 645--654, Aug. 1998.
[5]
Cadence Products: NanoRoute, available by WWW at: "http://www.cadence.com/products/nanorouteultra.html".
[6]
M. Hanan, "On Steiner's Problem with Rectilinear Distance," SIAM J. Applied Math., vol. 14, no. 2, pp. 255--265, Feb. 1966.
[7]
F. Rubin, "The Lee path connection algorithm," IEEE Trans. Computers, pp. 907--914, Sept. 1974.
[8]
A. Kahng and G. Robins, "On Optimal Interconnects for VLSI," Kluwer Academic, Boston, MA, 1995.
[9]
M. I. Shamos and D. Hoey, "Geometric intersection problems," 17th Annual Symposium on Foundations of Computer Science, IEEE, 1976.
[10]
Ulrich Lauter: "An O(NlogN) algorithm for Boolean Mask Operations," ACM IEEE 18th Design Automation Conference Proc., pp. 555--562, 1981.
[11]
Synopsys Products: Raphael Datasheet, available by WWW at: "http://www.synopsys.com/products/mixedsignal/raphael_ds.pdf.

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cover image ACM Conferences
ASP-DAC '04: Proceedings of the 2004 Asia and South Pacific Design Automation Conference
January 2004
957 pages
ISBN:0780381750

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IEEE Press

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Published: 27 January 2004

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