A static and dynamic energy reduction technique for I-cache and BTB in embedded processors

ABSTRACT

Power consumption is becoming one of the most important constraints for embedded processor design in nano-meter-scale technologies. Especially, as the transistor supply voltage and threshold voltage are scaled down, leakage energy consumption is increased even when the transistor is not switching. This paper proposes to use the loop cache to reduce static energy consumption as well as dynamic one. We combine it with CMOS circuits having sleep mode, and thus instruction cache can go to sleep mode when the loop cache is active. Detailed simulation shows that we can reduce static energy consumed by I-cache by up to 37.9%. We also propose to apply the technique to branch target buffer, and its static and dynamic energy consumption is reduced by up to 40.4% and 40.7%, respectively.

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