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Will the ASIC survive?

Published: 04 September 2004 Publication History

Abstract

ASIC design starts have declined lately and many voices speak of fundamental changes as a result of increasing design costs, predicting even the extinction of ASIC design altogether. ASICs and ASSPs have been a formidable economic force, accounting for over one third of the semiconductor market. Standard cell based designs have also been the major consumer of EDA tools and design technology. However, raising NRE costs which stand at approximately $10M to design an ASIC at the 130nm technology node, cost of re-spins, lack of flexibility (compared to programmable solutions) and increasing time to market have prompted the search for other design styles. These include structured ASICs, FPGAs, processor arrays and "platforms", which are all trying to fill the void left by the slowing of ASIC design starts. The reality however is that none has so far proven to be a solution with a wide spectrum of applications, because they are either a limited economic choice or because their performance constraints the application space. This presentation addresses the trade-offs among these design solutions and also looks at several ways of mixing these technologies. These alternative solutions are reviving cell-based design by adding the flexibility of those alternative solutions to traditional ASIC design.

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  • (2006)A methodology for FPGA to structured-ASIC synthesis and verificationProceedings of the conference on Design, automation and test in Europe: Designers' forum10.5555/1131355.1131369(64-69)Online publication date: 6-Mar-2006
  • (2006)A Highly Compatible Architecture Design for Optimum FPGA to Structured-ASIC Migration2006 IEEE International Conference on Semiconductor Electronics10.1109/SMELEC.2006.381114(506-510)Online publication date: Nov-2006
  • (2006)A Methodology for FPGA to Structured-ASIC Synthesis and VerificationProceedings of the Design Automation & Test in Europe Conference10.1109/DATE.2006.243775(1-6)Online publication date: 2006

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cover image ACM Conferences
SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design
September 2004
296 pages
ISBN:1581139470
DOI:10.1145/1016568
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 04 September 2004

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Cited By

View all
  • (2006)A methodology for FPGA to structured-ASIC synthesis and verificationProceedings of the conference on Design, automation and test in Europe: Designers' forum10.5555/1131355.1131369(64-69)Online publication date: 6-Mar-2006
  • (2006)A Highly Compatible Architecture Design for Optimum FPGA to Structured-ASIC Migration2006 IEEE International Conference on Semiconductor Electronics10.1109/SMELEC.2006.381114(506-510)Online publication date: Nov-2006
  • (2006)A Methodology for FPGA to Structured-ASIC Synthesis and VerificationProceedings of the Design Automation & Test in Europe Conference10.1109/DATE.2006.243775(1-6)Online publication date: 2006

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