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Leakage power optimization in standard-cell designs

Published: 04 September 2004 Publication History

Abstract

Leakage power consumption is a growing concern in integrated circuit design. Nanometer CMOS transistors are characterized by significant sub-threshold and gate leakage currents and feature size scaling is exacerbating this problem. In today's technologies (i.e., 90nm), sub-threshold leakage currents are still dominant with respect to gate currents (although the trend shows that the latter grows more rapidly as technology scales).In this talk, we will introduce a complete methodology for sub-threshold leakage current reduction based on the concept of sleep transistor insertion. Our insertion approach is layout-aware and it is fully compatible with industry-standard row-based layout styles and the supporting design tools. Sleep transistor cells are chosen from a library of cells that has been designed for high layout efficiency. These cells are inserted at the boundaries of existing cell rows, causing minimal disruption in placement and routing. The methodology ensures tight control of area and delay overheads, as it allows to selectively choose which gates in the netlist will be connetcted to the sleep transistors.The effectiveness of the sleep transistor insertion methodology has been benchmarked on a set of design examples for which a physical implementation was obtained through commercial EDA tools; the results we have achieved show a reduction of leakage power ranging from 74% to 83%, depending on the circuit.

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cover image ACM Conferences
SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design
September 2004
296 pages
ISBN:1581139470
DOI:10.1145/1016568
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 04 September 2004

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