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Verification and test challenges in SoC designs

Published: 04 September 2004 Publication History

Abstract

SoC (System-on-Chip) designs have introduced several new challenges for the functional verification and test disciplines. Besides the ever-growing functional complexity, we need to manage from several clock domains and low-power modes to all sorts of IP blocks like processors, complex peripherals, analog functions and different kinds of embedded memories. The reuse of 3rd party IP may help accelerating the design of new products, but it usually does not help the functional verification and it may even add to its complexity. Also, the same die may be used in several packages with different number of pins and bond-out options. This presentation will discuss these and other verification and test challenges. It also describes what tools, techniques and methodologies the industry is currently using to cope with them, and finalizes outlining some future directions.

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  • (2005)A Clock Isolation Method For Complex SoC Designs2005 Joint 30th International Conference on Infrared and Millimeter Waves and 13th International Conference on Terahertz Electronics10.1109/SOCC.2005.1554505(251-256)Online publication date: 2005
  • (2005)A methodology aimed at better integration of functional verification and RTL designDesign Automation for Embedded Systems10.1007/s10617-006-9587-610:4(285-298)Online publication date: 1-Dec-2005

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cover image ACM Conferences
SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design
September 2004
296 pages
ISBN:1581139470
DOI:10.1145/1016568
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 04 September 2004

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Cited By

View all
  • (2005)A Clock Isolation Method For Complex SoC Designs2005 Joint 30th International Conference on Infrared and Millimeter Waves and 13th International Conference on Terahertz Electronics10.1109/SOCC.2005.1554505(251-256)Online publication date: 2005
  • (2005)A methodology aimed at better integration of functional verification and RTL designDesign Automation for Embedded Systems10.1007/s10617-006-9587-610:4(285-298)Online publication date: 1-Dec-2005

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