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PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems

Published: 04 September 2004 Publication History

Abstract

Dynamically and Partially Reconfigurable Systems (DRSs) are those where any portion of the hardware behavior can be altered at application execution time. These systems have the potential to provide hardware with flexibility similar to that of software, while leading to better performance and smaller system size. However, the widespread acceptance of DRSs depends on adequate support to design and implement them. This work proposes a framework for DRS design and implementation named PADReH. The approach is compared to other propositions available in the literature. The first steps of the framework implementation are described, involving methods and tools to control the hardware reconfiguration process and the generation of partial bitstreams. The main contribution of the work is to provide means to systematically reduce the lack of support currently hampering the adoption of DRSs as a mainstream technology.

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Cited By

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  • (2017)Partial dynamic reconfiguration framework for FPGAs through remote accessInternational Journal of High Performance Systems Architecture10.5555/3160670.31606747:2(98-104)Online publication date: 1-Jan-2017
  • (2015)Mapping adaptive hardware systems with partial reconfiguration using CoPR for Zynq2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)10.1109/AHS.2015.7231169(1-8)Online publication date: Jun-2015
  • (2013)An FPGA Router for Alternative Reconfiguration FlowsProceedings of the 2013 IEEE 27th International Symposium on Parallel and Distributed Processing Workshops and PhD Forum10.1109/IPDPSW.2013.221(163-171)Online publication date: 20-May-2013
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cover image ACM Conferences
SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design
September 2004
296 pages
ISBN:1581139470
DOI:10.1145/1016568
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 04 September 2004

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Author Tags

  1. dynamically and partially reconfigurable systems
  2. partial bitstream generation
  3. reconfiguration control
  4. run-time reconfiguration

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Cited By

View all
  • (2017)Partial dynamic reconfiguration framework for FPGAs through remote accessInternational Journal of High Performance Systems Architecture10.5555/3160670.31606747:2(98-104)Online publication date: 1-Jan-2017
  • (2015)Mapping adaptive hardware systems with partial reconfiguration using CoPR for Zynq2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)10.1109/AHS.2015.7231169(1-8)Online publication date: Jun-2015
  • (2013)An FPGA Router for Alternative Reconfiguration FlowsProceedings of the 2013 IEEE 27th International Symposium on Parallel and Distributed Processing Workshops and PhD Forum10.1109/IPDPSW.2013.221(163-171)Online publication date: 20-May-2013
  • (2010)Run-time mapping for dynamic reconfiguration management in embedded systemsInternational Journal of Embedded Systems10.1504/IJES.2010.0390314:3/4(276)Online publication date: 2010
  • (2010)Modern development methods and tools for embedded reconfigurable systemsIntegration, the VLSI Journal10.1016/j.vlsi.2009.06.00243:1(1-33)Online publication date: 1-Jan-2010
  • (2009)ReferencesReconfigurable System Design and Verification10.1201/9781420062670.bmatt(225-244)Online publication date: 10-Nov-2009
  • (2009)Slotless module-based reconfiguration of embedded FPGAsACM Transactions on Embedded Computing Systems10.1145/1596532.15965389:1(1-26)Online publication date: 29-Oct-2009
  • (2009)Modeling reconfiguration in a FPGA with a hardwired network on chip2009 IEEE International Symposium on Parallel & Distributed Processing10.1109/IPDPS.2009.5161213(1-8)Online publication date: May-2009
  • (2008)A Flexible system level design methodology targeting run-time reconfigurable FPGAsEURASIP Journal on Embedded Systems10.5555/1340444.13879852008(1-18)Online publication date: 1-Jan-2008
  • (2008)Part-E - A Tool for Reconfigurable System DesignProceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs10.1109/ReConFig.2008.64(199-204)Online publication date: 3-Dec-2008
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