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Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration

Published: 04 September 2004 Publication History

Abstract

Xilinx Virtex FPGAs offer the possibility of dynamic and partial run-time reconfiguration. If a system uses this feature the designer has to take care, that no signal lines cross the border to other reconfigurable regions. Traditional solutions connecting modules on a dynamic and partial reconfigurable system use TBUF elements for connection and separation of the functional blocks. While automalically placing and routing the design, the routing-tool sometimes uses signal lines which cross the module border. The constraints given by the designer are ignored. To solve this problem we use slices instead of TBUF elements which leads to a benefit by using an automatic modular design flow. This paper gives an overview of the used technique and the complete system on a Xilinx XC2V3000 FPGA.

References

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J. Becker, M. Huebner, M. Ullmann: "Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-offs and Limitations", SBCCI03, Sao Paulo, Sep. 03
[2]
J. Becker, M. Huebner, M. Ullmann: "Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations", VLSI03, Darmstadt, Sep. 03
[3]
L. Benini, G. De Micheli: "Networks on Chip: A New Paradigm for Systems on Chip Design", Date 02, March 3 7, Paris France
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B. Blodget, S. McMillan: "A lightweight approach for embedded reconfiguration of FPGAs", Date03, Munich Germany
[5]
M. Huebner, M. Ullmann, F. Weissel, J. Becker: "Real-time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration", RAW04, Santa Fee
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J.C. Palma, A. Vieira de Melo, F. G. Moraes, N. Calazans, "Core Communication Interface for FPGAs", SBCCI02, Porto Alegre BRAZIL
[7]
M. Ullmann, M. Huebner, B. Grimm, J. Becker: "An FPGA Run-Time System for Dynamical On-Demand Reconfiguration", RAW04, Santa Fee
[8]
http://www.vector-cantech.com
[9]
http://www.xilinx.com/ise/design_tools/
[10]
http://www.xilinx.com/ise/embedded/edk.htm
[11]
http://www.xilinx.com/ipcenter/processor_central/microblaze/literature.htm
[12]
XAPP290: Two Flows for Partial Reconfiguration: Module Based or Small Bit Manipulations

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  1. Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration

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      cover image ACM Conferences
      SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design
      September 2004
      296 pages
      ISBN:1581139470
      DOI:10.1145/1016568
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 04 September 2004

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      Author Tags

      1. dynamic partial reconfiguration
      2. virtex

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      • (2014)Reconfigurable Multiprocessor SystemsACM SIGARCH Computer Architecture News10.1145/2693714.269372242:4(39-44)Online publication date: 3-Dec-2014
      • (2014)Leveraging partial dynamic reconfiguration on Zynq SoC FPGAs2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2014.6861353(1-6)Online publication date: May-2014
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      • (2012)A Survey of FPGA Dynamic Reconfiguration Design Methodology and ApplicationsInternational Journal of Embedded and Real-Time Communication Systems10.4018/jertcs.20120401023:2(23-39)Online publication date: 1-Apr-2012
      • (2012)A dynamically reconfigurable communication architecture for multicore embedded systemsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2012.02.00358:3-4(140-159)Online publication date: 1-Mar-2012
      • (2012)Run-time generation of partial FPGA configurationsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2011.10.00158:1(24-37)Online publication date: 1-Jan-2012
      • (2012)Architecture and operating system support for two-dimensional runtime partial reconfigurationThe Journal of Supercomputing10.1007/s11227-010-0457-459:2(610-635)Online publication date: 1-Feb-2012
      • (2011)Co-managing software and hardware modules through the Juggle middlewareProceedings of the 12th International Middleware Conference10.5555/2414338.2414368(420-439)Online publication date: 12-Dec-2011
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