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Exception handling in microprocessors using assertion libraries

Published: 04 September 2004 Publication History

Abstract

In complex System-on-a-Chip (SoC) designs, designers often need to add new features into an original processor core, such as to extend the exception handling mechanism to consider exceptions in the remaining portion of the SoC design. We present in this paper a scalable architecture that can be used to add complex exception handling mechanisms in processor cores and how it can be used to extend the fixed set of exceptions found in microprocessor cores. This mechanism is based on the use of assertion libraries linked by an assertion processor to incorporate these new functionalities.

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  1. Exception handling in microprocessors using assertion libraries

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      cover image ACM Conferences
      SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design
      September 2004
      296 pages
      ISBN:1581139470
      DOI:10.1145/1016568
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      New York, NY, United States

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      Published: 04 September 2004

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      Author Tags

      1. assertions
      2. exceptions handling

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      • (2014)Related WorkDebugging Systems-on-Chip10.1007/978-3-319-06242-6_9(235-255)Online publication date: 15-Jul-2014
      • (2012)An infrastructure for debug using clusters of assertion-checkersMicroelectronics Reliability10.1016/j.microrel.2012.04.01652:11(2781-2798)Online publication date: Nov-2012
      • (2008)Integration of Hardware Assertions in Systems-on-Chip2008 IEEE International Test Conference10.1109/TEST.2008.4700593(1-10)Online publication date: Oct-2008
      • (2007)Assertion based design error diagnosis for core-based SoCs2007 IEEE International SOC Conference10.1109/SOCC.2007.4545472(269-272)Online publication date: Sep-2007
      • (2007)On-Chip Verification of NoCs Using Assertion Processors10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)10.1109/DSD.2007.4341519(535-538)Online publication date: Aug-2007

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