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A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35͘m CMOS technology

Published: 04 September 2004 Publication History

Abstract

The design of a dual modulus prescaler 32/33 in a 0.35μm CMOS technology is presented. The prescaler is a circuit employed in high frequency synthesizer designs. In the proposed circuit the technique called Extended True Single Phase Clock (E-TSPC), an extension of the True Single Phase Clock (TSPC) technique, was applied. Additionally some new structures to double the data output rate are also employed. Simulations, based on the prescaler layout, were carried out and the results indicate that the circuit can reach up to 4 GHz with 4.38 mW of power consumption and power supply of 3.3 V.

References

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Argüello. A.M.G. Estudo e Projeto de um sintetizador de freqüência para RF em tecnologia CMOS de 0,35͘m. Ms. Dissertation, Department of Eletronic Systems Engineering, University of São Paulo, São Paulo, Brazil, 2003 (in portuguese)
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Yuan, J.-R and Svensson. C. High speed CMOS circuit technique. IEEE J. Solid-State Circuits, 24, 1 (Feb 1989), 62--70.
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Navarro, J. and Van Noije, W. E-TSPC: Extended True Single Phase Clock CMOS circuit technique for high speed applications. SBMICRO J. Solid-State Devices and Circuits, 5, 2 (1997), 21--26.
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Navarro, J. Técnicas para projetos de ASICs CMOS de alta velocidade. PhD. Thesis, Department of Eletronic Systems Engineering, University of São Paulo, São Paulo, Brazil. 1998 (in portuguese).
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Navarro, J. and Van Noije, W. A 1.6-GHz dual modulus prescaler using the Extended True-Single-Phase-Clock CMOS circuit tecnique (E-TSPC). IEEE J. Solid-State Circuits. 34, 1 (Jan. 1999), 97--102.
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Navarro, J., and Van Noije, W. Extended TSPC structures with double input/output data throughput for Gigahertz CMOS circuit design. IEEE Trans. on VLSI Systems, 10, 3 (June 2002), 301--308.
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Chang, B., Park, J., and Kim, W. A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops. IEEE J. Solid-State Circuits, 31, 5 (May 1996), 749--752.
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Yang, C.-Y., Dehng, G.-K., Hsu, J.-M., and Liu, S.-I. New dynamic flip-flops for high-speed dual-modulus prescaler. IEEE J. Solid-State Circuits, 33, 10 (Oct. 1998), 1568--1571.
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Yan, H, Biyani, M., O, K. K. A high-speed CMOS dual-phase dynamic-pseudo NMOS ((DP)2 latch and its application in a dual-modulus prescaler. IEEE J. Solid-State Circuits, 34, 10 (Oct. 1999), 1400--1404.
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Craninckx, J., and Steyaert. M.S.J. A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7 um CMOS. IEEE J. Solid-State Circuits, 31, 7 (July, 1996), 890--897.

Cited By

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  • (2023)Area and power efficient divide-by-32/33 dual-modulus pre-scaler using split-path TSPC with AVLS for frequency dividerJournal of Electrical Engineering10.2478/jee-2023-004874:5(403-412)Online publication date: 21-Oct-2023
  • (2020)A 4.1 GHz–9.2 GHz Programmable Frequency Divider for Ka Band PLL Frequency SynthesizerElectronics10.3390/electronics91117739:11(1773)Online publication date: 26-Oct-2020
  • (2016)A 5GHz 1.2V divide-by-128/129 and 256/257 dual modulus prescalers using 90nm CMOS technology2016 2nd International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB)10.1109/AEEICB.2016.7538409(115-120)Online publication date: Feb-2016
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  1. A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35͘m CMOS technology

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    cover image ACM Conferences
    SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design
    September 2004
    296 pages
    ISBN:1581139470
    DOI:10.1145/1016568
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 04 September 2004

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    Author Tags

    1. TSPC
    2. high speed digital circuit
    3. low power
    4. prescaler

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    View all
    • (2023)Area and power efficient divide-by-32/33 dual-modulus pre-scaler using split-path TSPC with AVLS for frequency dividerJournal of Electrical Engineering10.2478/jee-2023-004874:5(403-412)Online publication date: 21-Oct-2023
    • (2020)A 4.1 GHz–9.2 GHz Programmable Frequency Divider for Ka Band PLL Frequency SynthesizerElectronics10.3390/electronics91117739:11(1773)Online publication date: 26-Oct-2020
    • (2016)A 5GHz 1.2V divide-by-128/129 and 256/257 dual modulus prescalers using 90nm CMOS technology2016 2nd International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB)10.1109/AEEICB.2016.7538409(115-120)Online publication date: Feb-2016
    • (2011)Optimization and design of a novel prescaler and its application to GPS receiversScience China Information Sciences10.1007/s11432-011-4206-y54:9(1938-1944)Online publication date: 28-Feb-2011
    • (2011)A Gigahertz Digital CMOS Divide-by-N Frequency Divider Based on a State Look-Ahead StructureCircuits, Systems, and Signal Processing10.1007/s00034-011-9279-830:6(1549-1572)Online publication date: 1-Dec-2011
    • (2010)Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 PrescalerIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2009.201618357:1(72-82)Online publication date: Jan-2010

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