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ATPG for fault diagnosis on analog electrical networks using evolutionary techniques

Published: 04 September 2004 Publication History

Abstract

This paper proposes a method for automated test pattern generation for fault diagnosis on continuous-time analog electrical networks based on evolutionary techniques. The paper states a method for coding a generic algorithm, based on a given heuristic, that are able to generate a set of optimum frequencies capable to disclose parametric faults. The method itself is generic, and not based on specific or ad hoc features at all.

References

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Holland, J. H.: Adaptation in natural and artificial systems. Ann Arbor: The University of Michigan Press, 1975.
[2]
Rechenberg, I.: Evolutionsstrategie - Optimierung technischer Systeme nach Prinzipien der biologischen Evolution. Stuttgart: Frommann-Holzboog, 1973.
[3]
Fogel, L. J., Owens, A. J. and Walsh, M. J.: Artificial Intelligence through Simulated Evolution. New York: John Wiley, 1966.
[4]
Prinetto, P., M. Rebaudengo, M. Sonza Reorda, An Automatic Test Pattern Generator for Large Sequential Circuits based on GAs, ITC'94.
[5]
Mesquita Filho, A.C.-Chromosome Representation through Adjacency Matrix in Evolutionary Circuits Synthesis. Proc of the NASA/DoD Conf. on Evolvable Hardware, 2002.
[6]
Savioli, C.E.F, Szendrodi, C. E.,Calvano, J.V.; Mesquita Filho, A.C.; Lubaszewski. A Rank-Based Genetic Algorithm for Fault Tolerant Analog Circ. Synth.,LATW'03.
[7]
Calvano, J.V., Lubaszewki, M., Alves, V.C., Fault Models and Test Generation for OpAmp Circuits - The FFM; JETTA, 17, Kluwer Academic Pub. Netherlands - 2001.
[8]
Zebulum, Ricardo S. et al.-Evolutionary Electronics- Automatic Design of Circ.& Syst. by Genetic Algorithms. CRC Press, 20002.
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Lohn, Jason D. et al.-A Circuit Representation Technique for Automated Circuit Design-IEEE Trans. on Evolutionary Comp. Vol.3, No. 3, Sep 99.
[10]
Savioli, C.E., C.C.Szendrodi, J.V. Calvano & M. S. Lubaszewski, The Use of Evolutionary Circuits for Designing for Robustness Analog Circuits, IMSTW'03.
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Calvano, J.V., Alves, V.C, Lubaszewski, M. S., Fault Detection Methodology and BIST Method for 2nd Order Butterworth, Chebyshev and Bessel Filter Approximations. 17th VTS'00.

Cited By

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  • (2012)A Novel TOPSIS-Based Test Vector Compaction Technique for Analog Fault DetectionJournal of Electronic Testing: Theory and Applications10.1007/s10836-012-5311-628:4(535-540)Online publication date: 1-Aug-2012
  • (2006)An Immune Fault Detection System for Analog Circuits with Automatic Detector Generation2006 IEEE International Conference on Evolutionary Computation10.1109/CEC.2006.1688682(2966-2972)Online publication date: 2006
  • (2005)Fault-Trajectory Approach for Fault Diagnosis on Analog CircuitsProceedings of the conference on Design, Automation and Test in Europe - Volume 110.1109/DATE.2005.154(174-175)Online publication date: 7-Mar-2005

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  1. ATPG for fault diagnosis on analog electrical networks using evolutionary techniques

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      cover image ACM Conferences
      SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design
      September 2004
      296 pages
      ISBN:1581139470
      DOI:10.1145/1016568
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 04 September 2004

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      Author Tags

      1. analog and mixed-signal test
      2. automatic test pattern generation
      3. fault models
      4. genetic algorithms

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      View all
      • (2012)A Novel TOPSIS-Based Test Vector Compaction Technique for Analog Fault DetectionJournal of Electronic Testing: Theory and Applications10.1007/s10836-012-5311-628:4(535-540)Online publication date: 1-Aug-2012
      • (2006)An Immune Fault Detection System for Analog Circuits with Automatic Detector Generation2006 IEEE International Conference on Evolutionary Computation10.1109/CEC.2006.1688682(2966-2972)Online publication date: 2006
      • (2005)Fault-Trajectory Approach for Fault Diagnosis on Analog CircuitsProceedings of the conference on Design, Automation and Test in Europe - Volume 110.1109/DATE.2005.154(174-175)Online publication date: 7-Mar-2005

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