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Adaptive DMA-based I/O interfaces for data stream handling in multi-grained reconfigurable hardware architectures

Published: 04 September 2004 Publication History

Abstract

Modern application scenarios out of multimedia and mobile communication domains demand more and more performant data processing architectures, which cannot be achieved by using current DSP or microprocessor approaches. This contribution describes a new architecture approach out of the reconfigurable array field which offers a set of new features to increase the flexibility and usability of reconfigurable array architectures by increasing the performance benefit concurrently and decreasing the communication overhead caused by the system controller by managing the architecture. The main focus of this publication is I/O interface where the authors will discuss the concepts in detail memory. By this approach the architecture gets concept specific advantages and disadvantages. Basically, in combination with random access memories sequential execution processors are predestinated for processing of control oriented application. The disadvantages of this kind of approaches lie in the frequently memory accesses during instruction/data reading and writing. Thereby this strategy leads inevitable to a bandwidth bottleneck which results because of a brisk data exchange between the memory and data processing unit. Modern microprocessors reduce this problem by deploying fast clocked caches. By working on streaming data the caches loose their potency and the throughput of the data processing unit converges to maximum memory throughput, which limits the system performance.

References

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Juergen Becker, Thilo Pionteck, Manfred Glesner: DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communication Applications; 10th International Conference on Field Programmable Logic and Applications, Villach, Osterreich, 2000.]]
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Becker, J.; Hartenstein, R. Configware and Morphware going Mainstream; Elsevier Journal of Systems Architecture JSA (Special Issue on Reconfigurable Systems), Oktober 2003.]]
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Becker, J.; Thomas, A.; Scheer, M.: Datapath and Compiler Integration of Coarse-grain Reconfigurable XPP-Arrays into Pipelined RISC Processors; Proceedings of IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC 2003), Darmstadt, Germany, Dezember 1-3, 2003]]
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Cited By

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  • (2007)New Adaptive Multi-grained Hardware Architecture for Processing of Dynamic Function Patterns (Neue adaptive multi-granulare Hardwarearchitektur)it - Information Technology10.1524/itit.2007.49.3.16549:3Online publication date: 1-Jan-2007
  • (2005)Multi-Grained Reconfigurable Datapath Structures for Online-Adaptive Reconfigurable Hardware ArchitecturesProceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design10.1109/ISVLSI.2005.51(118-123)Online publication date: 11-May-2005
  • (2005)Design of a dynamic reconfigurable multi-grained hardware architecture with adaptive runtime routingInternational Conference on Field Programmable Logic and Applications, 2005.10.1109/FPL.2005.1515836(745-746)Online publication date: 2005

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cover image ACM Conferences
SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design
September 2004
296 pages
ISBN:1581139470
DOI:10.1145/1016568
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 04 September 2004

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Author Tags

  1. HoneyComb architecture
  2. adaptive I/O interfaces
  3. data stream handling
  4. multi-grained reconfigurable hardware architecture

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Cited By

View all
  • (2007)New Adaptive Multi-grained Hardware Architecture for Processing of Dynamic Function Patterns (Neue adaptive multi-granulare Hardwarearchitektur)it - Information Technology10.1524/itit.2007.49.3.16549:3Online publication date: 1-Jan-2007
  • (2005)Multi-Grained Reconfigurable Datapath Structures for Online-Adaptive Reconfigurable Hardware ArchitecturesProceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design10.1109/ISVLSI.2005.51(118-123)Online publication date: 11-May-2005
  • (2005)Design of a dynamic reconfigurable multi-grained hardware architecture with adaptive runtime routingInternational Conference on Field Programmable Logic and Applications, 2005.10.1109/FPL.2005.1515836(745-746)Online publication date: 2005

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