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Enhanced 32-bit carry lookahead adder using multiple output enable-disable CMOS differential logic

Published: 04 September 2004 Publication History

Abstract

This paper presents an enhanced 32-bit carry look-ahead (CLA) adder implemented using the multi-output enable /disable CMOS differential logic (MOECDL) style. The MOECDL structure proposed represents a promising technique for iterative networks and self-timed circuits. The recursive property of CLA algorithm has been efficiently exploited to demonstrate the advantages of multiple-output structures. The 32-bit MOECDL CLA circuit has been designed into a standard 0.5mm CMOS technology. Comparison to the known DCVS style is presented through electrical simulation.

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      cover image ACM Conferences
      SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design
      September 2004
      296 pages
      ISBN:1581139470
      DOI:10.1145/1016568
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      Published: 04 September 2004

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      Author Tags

      1. CMOS
      2. ECDL
      3. adder
      4. digital circuits

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      • (2018)Realization of High Speed Low Power MCC Adder using Dynamic CMOS Transistors2018 International Conference on Current Trends towards Converging Technologies (ICCTCT)10.1109/ICCTCT.2018.8551171(1-5)Online publication date: Mar-2018
      • (2017)Performance Comparison of 64-bit Carry Look-Ahead Adders Using 32nm CMOS TechnologyMaterials Today: Proceedings10.1016/j.matpr.2017.02.1184:2(4153-4168)Online publication date: 2017
      • (2015)High speed Manchester Carry chain with carry-skip capability2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015]10.1109/ICCPCT.2015.7159396(1-7)Online publication date: Mar-2015
      • (2015)Video sharing on OSNs using a distributed algorithm2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015]10.1109/ICCPCT.2015.7159343(1-4)Online publication date: Mar-2015
      • (2015)A high speed 256-bit carry look ahead adder design using 22nm strained silicon technology2015 2nd International Conference on Electronics and Communication Systems (ICECS)10.1109/ECS.2015.7124884(174-179)Online publication date: Feb-2015
      • (2015)A Low-Power High-Speed Double Manchester Carry Chain with Carry-Skip Using D3LProceedings of the Second International Conference on Computer and Communication Technologies10.1007/978-81-322-2526-3_4(25-34)Online publication date: 11-Sep-2015
      • (2013)New High-Speed Multioutput Carry Look-Ahead AddersIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2013.227808860:10(667-671)Online publication date: Oct-2013
      • (2006)Evaluation of Dual-Rail CMOS Logic Styles for Self-Timed Circuits2006 NORCHIP10.1109/NORCHP.2006.329209(197-200)Online publication date: Nov-2006

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