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A multi-standard channel-decoder for base-station applications

Published: 04 September 2004 Publication History

Abstract

In this paper, a VLSI implementation of a multi-standard channel-decoder for EDGE, WCDMA, and CDMA2k convolutional-codes is presented. The new architecture employs the MAP algorithm for convolutional decoding to support soft-outputs.The decoder is designed for base-station applications. The maximum throughput of the decoder is 16 Mbps for WCDMA and CDMA2k, and 70 Mbps for EDGE, at a clock frequency of 200 MHz.

References

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Third Generation Partnership Project, "3GPP home page," www.3gpp.org.
[2]
F. Berens, G. Kreiselmaier, and N. Wehn, "Channel Decoder Architecture for 3G Mobile Wireless Terminals," in Proc. 2004 Design, Automation and Test in Europe (DATE '04), Paris, France, Feb. 2004, Accepted for Publication.
[3]
M. A. Bickerstaff, D. Garrett, T. Prokop, C. Thomas, B. Widdup, G. Zhou, L. M. Davis, G. Woodward, C. Nicol, and R. Yan, "A Unified Turbo/Viterbi Channel Decoder for 3GPP Mobile Wireless in 0.18-um CMOS," IEEE Journal of Solid-State Circuits, vol. 37, no. 11, pp. 1555--1564, Nov. 2002.
[4]
China Communications Standard Association, "CCSA home page," www.cwts.org.
[5]
Third Generation Partnership Project 2, "3GPP2 home page," www.3gpp2.org.
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M. Tuchler, R. Koetter, and A. Singer, "Turbo equalization: principles and new results," IEEE Transactions on Communications, vol. 50, pp. 754--767, May 2002.
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J. Hagenauer and P. Hoeher, "A Viterbi Algorithm with Soft-Decision Outputs and its Applications," in Proc. 1989 Global Telecommunications Conference (Globecom '89), Dallas, Texas, USA, Nov. 1989, pp. 1680--1686.
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J. Vogt, K. Koora, A. Finger, and G. Fettweis, "Comparison of Different Turbo Decoder Realizations for IMT-2000," in Proc. 1999 Global Telecommunications Conference (Globecom '99), Rio de Janeiro, Brazil, Dec. 1999, vol. 5, pp. 2704--2708.
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G. Kreiselmaier, Efficient VLSI Architectures for Multi-mode Channel Decoder, Ph.D. thesis, Institute of Microelectronic Systems, Department of Electrical Engineering and Information Technology, University of Kaiserslautern, 2003.
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P. Robertson, P. Hoeher, and E. Villebrun, "Optimal and Sub-Optimal Maximum a Posteriori Algorithms Suitable for Turbo Decoding," European Transactions on Telecommunications (ETT), vol. 8, no. 2, pp. 119--125, March--April 1997.
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H. Dawid, G. Gehnen, and H. Meyr, "MAP Channel Decoding: Algorithm and VLSI Architecture," in VLSI Signal Processing VI, pp. 141--149. IEEE, 1993.
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ARM, "AMBA Specification, rev. 2.0, May 1999," http://www.arm.com.

Cited By

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  • (2011)Architecture and Hardware RequirementsError Control Coding for B3G/4G Wireless Systems10.1002/9780470975220.ch4(113-188)Online publication date: 9-Mar-2011
  • (2009)FEC Decoders for FutureWireless Devices: Scalability Issues and Multi-standard CapabilitiesCircuits and Systems for Future Generations of Wireless Communications10.1007/978-1-4020-9917-5_12(271-297)Online publication date: 2009
  • (2008)A reconfigurable ASIP for convolutional and turbo decoding in an SDR environmentIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.5555/1515843.151584916:10(1309-1320)Online publication date: 1-Oct-2008
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  1. A multi-standard channel-decoder for base-station applications

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    cover image ACM Conferences
    SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design
    September 2004
    296 pages
    ISBN:1581139470
    DOI:10.1145/1016568
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 04 September 2004

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    Author Tags

    1. CDMA2k
    2. MAP
    3. W-CDMA
    4. configurable
    5. convolutional decoder
    6. hardware sharing
    7. wireless

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    Cited By

    View all
    • (2011)Architecture and Hardware RequirementsError Control Coding for B3G/4G Wireless Systems10.1002/9780470975220.ch4(113-188)Online publication date: 9-Mar-2011
    • (2009)FEC Decoders for FutureWireless Devices: Scalability Issues and Multi-standard CapabilitiesCircuits and Systems for Future Generations of Wireless Communications10.1007/978-1-4020-9917-5_12(271-297)Online publication date: 2009
    • (2008)A reconfigurable ASIP for convolutional and turbo decoding in an SDR environmentIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.5555/1515843.151584916:10(1309-1320)Online publication date: 1-Oct-2008
    • (2008)A reconfigurable application specific instruction set processor for convolutional and turbo decoding in a SDR environmentProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403388(38-43)Online publication date: 10-Mar-2008
    • (2008)A Reconfigurable ASIP for Convolutional and Turbo Decoding in an SDR EnvironmentIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200242816:10(1309-1320)Online publication date: Oct-2008
    • (2008)A Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR Environment2008 Design, Automation and Test in Europe10.1109/DATE.2008.4484657(38-43)Online publication date: Mar-2008

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