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FPGA implementation of parallel turbo-decoders

Published: 04 September 2004 Publication History

Abstract

Wireless communication penetrates more and more areas of our everyday lives. Turbo-Codes provide good forward-error correction to improve the data transfer reliability. They are used in current standards and future system designers considers them promising candidates. Dedicated hardware, however, is too expensive to use in a new and still rapidly changing system; due to the non-recurring engineering and mask costs.In this paper we therefore present a scalable Turbo-Decoder architecture targeted towards FPGA implementation for low-volume devices. It allows to optimally exploit the given hardware resources on FPGA to match the desired system throughput. Our design is ported to the Xilinx Virtex-II family. On the Virtex-II 3000, we achieve a maximum throughput of 26Mbit/s at 84MHz with a latency of 185μs.

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A. Nimbalker, K. T. Blankenship, B. Classon, T. E. Fuja, and D. J. Costello, "Inter-Window Shuffle Interleavers for High Throughput Turbo Decoding," in Proc. 3nd International Symposium on Turbo Codes & Related Topics, Brest, France, Sept. 2003, pp. 355--358.
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M. J. Thul, F. Gilbert, and N. Wehn, "Optimized Concurrent Interleaving for High-Throughput Turbo-Decoding," in Proc. 9th IEEE International Conference on Electronics, Circuits and Systems (ICECS '02), Dubrovnik, Croatia, Sept. 2002, pp. 1099--1102.
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M. J. Thul, F. Gilbert, T. Vogt, G. Kreiselmaier, and N. Wehn, "A Scalable System Architecture for High-Throughput Turbo-Decoders," Journal of VLSI Signal Processing Systems (Special Issue on Signal Processing for Broadband Communications), vol. 39, no. 1/2, 2005, Kluwer Academic Publishers, Boston -- to appear.

Cited By

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  • (2019)A High Throughput Hardware Architecture for Parallel Recursive Systematic Convolutional EncodersInformation10.3390/info1004015110:4(151)Online publication date: 24-Apr-2019
  • (2016)High performance parallel turbo decoder with configurable interleaving network for LTE applicationIntegration, the VLSI Journal10.1016/j.vlsi.2015.05.00352:C(77-90)Online publication date: 1-Jan-2016
  • (2006)New Schemes in Clustered VLIW Processors Applied to Turbo DecodingProceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors10.1109/ASAP.2006.48(291-296)Online publication date: 11-Sep-2006
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    cover image ACM Conferences
    SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design
    September 2004
    296 pages
    ISBN:1581139470
    DOI:10.1145/1016568
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 04 September 2004

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    Author Tags

    1. FPGA implementation
    2. parallel architecture
    3. turbo-decoder
    4. wireless

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    View all
    • (2019)A High Throughput Hardware Architecture for Parallel Recursive Systematic Convolutional EncodersInformation10.3390/info1004015110:4(151)Online publication date: 24-Apr-2019
    • (2016)High performance parallel turbo decoder with configurable interleaving network for LTE applicationIntegration, the VLSI Journal10.1016/j.vlsi.2015.05.00352:C(77-90)Online publication date: 1-Jan-2016
    • (2006)New Schemes in Clustered VLIW Processors Applied to Turbo DecodingProceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors10.1109/ASAP.2006.48(291-296)Online publication date: 11-Sep-2006
    • (2005)A Configurable Application Specific Processor for Turbo DecodingConference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.10.1109/ACSSC.2005.1599985(1356-1360)Online publication date: 2005

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