skip to main content
10.1145/1016568.1016632acmconferencesArticle/Chapter ViewAbstractPublication PagessbcciConference Proceedingsconference-collections
Article

An improved synthesis method for low power hardwired FIR filters

Published: 04 September 2004 Publication History

Abstract

This work presents a method to design parallel digital finite impulse response (FIR) filters for hardwired (fixed coefficients) implementation with reduced number of adders and logic depth in the multiplier block. The proposed method uses a combination of two approaches: first, the reduction of the coefficients to N-Power-of-Two (NPT) terms, where N is the maximum number of bits in '1' state allowed for each coefficient and Common Subexpression Elimination (CSE) among multipliers. An algorithm for selecting the best NPT coefficient set for a given filter specification is proposed. Initially, a floating point coefficient set is generated using classical methods for FIR filters and then several sets of fixed point coefficients are generated by rounding the result of the floating point coefficients multiplied by a scale factor different for each set. The coefficient sets are then converted to NPT and a frequency response for each set is obtained. Based on the frequency response, the algorithm selects the best set. This set is then used as input for a CSE algorithm, which eliminate all common subexpressions among the multipliers and generates a hardware description of the filter in VHDL for synthesis purpose. The results show significant reduction in the number of adders and logic depth of the multiplier block with a minimal degradation in the filter transfer characteristics, showing the usefulness of the proposed method for low power design of parallel filters.

References

[1]
M. Potkonjak, M. B. Srivastava, and A. Chandrakasan, Efficient substitution of multiple Constant multiplication by shifts and addition using iterative pairwise matching. In Proc. 31st ACM/IEEE Design Antomation Conf., (1994), 189--194
[2]
M. Mehendale, S. D, Sherlekar, and G. Venkatesh, Syntesis of multiplier-less FIR filters with minimum number of additions, in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, (1995), 668--671
[3]
R. Pasko, P. Schaumont, V. Derudder, S. Vernalde, and D. Iuraekova. A new algorithm for elimination of common subexpressions, IEEE Trans. Computer-Aided Design, 18. (Jan 1999), 58--68.
[4]
H. Samueli, An improved search algorithm for the design of multiplier-less FIR filters with powers-of-two coefficients, IEE Trans. Circuits Syst., 36 (July 1989), 1044--1047.
[5]
K-H Chen, T-D Chiueh, Design and implementation of a reconfigurable FIR filter, Proc of 2003 Int. Symp. Circuits Systems, ISCAS '03, 3, (May 2003), 25--28.
[6]
K. Hwang, Computer arithmetic Principles, Architecture and Design: Wiley, 1979.
[7]
C. Lim, J. B. Evans, and B. Liu, Decomposition of binary integers into signed power-of-two terms, IEEE Trans. Circuits Syst., 38, (June 1991) 667--672.
[8]
J. Portela, E. Costa. J. Monteiro, Optimal Combination of Number of Taps and Coefficient Bit-Width for Low Power FIR Filter Realization, IEEE European Conference on Circuit Theory and Design. (Sep. 2003), 145--148.
[9]
ZHAO, Q.; TADOKORO, Y. A Simple Design of FIR Filters with Powers-of-Two Coefficients, IEEE Transactions on Circuits and Systems. 35, 5 (May, 1988).
[10]
R. W. Hamming, Digital Filters: 3rd ed, Prentice Hall, 1989.

Cited By

View all
  • (2019)Design of Low-Complexity FIR Filters Based on Signed-Powers-of-Two Coefficients With Reusable Common SubexpressionsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2007.89561526:10(1898-1907)Online publication date: 4-Jan-2019
  • (2018)Efficient Shift-Add Implementation of FIR Filters Using Variable Partition Hybrid Form StructuresIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2018.2838666(1-11)Online publication date: 2018
  • (2005)Performance evaluation of parallel FIR filter optimizations in ASICs and FPGA48th Midwest Symposium on Circuits and Systems, 2005.10.1109/MWSCAS.2005.1594393(1481-1484 Vol. 2)Online publication date: 2005

Index Terms

  1. An improved synthesis method for low power hardwired FIR filters

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design
    September 2004
    296 pages
    ISBN:1581139470
    DOI:10.1145/1016568
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 04 September 2004

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. FPGA synthesis
    2. common subexpression elimination
    3. parallel FIR filter
    4. power-of-two

    Qualifiers

    • Article

    Conference

    SBCCI04
    Sponsor:

    Acceptance Rates

    Overall Acceptance Rate 133 of 347 submissions, 38%

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)0
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 14 Feb 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2019)Design of Low-Complexity FIR Filters Based on Signed-Powers-of-Two Coefficients With Reusable Common SubexpressionsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2007.89561526:10(1898-1907)Online publication date: 4-Jan-2019
    • (2018)Efficient Shift-Add Implementation of FIR Filters Using Variable Partition Hybrid Form StructuresIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2018.2838666(1-11)Online publication date: 2018
    • (2005)Performance evaluation of parallel FIR filter optimizations in ASICs and FPGA48th Midwest Symposium on Circuits and Systems, 2005.10.1109/MWSCAS.2005.1594393(1481-1484 Vol. 2)Online publication date: 2005

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Figures

    Tables

    Media

    Share

    Share

    Share this Publication link

    Share on social media