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Advanced technology mapping for standard-cell generators

Published: 04 September 2004 Publication History

Abstract

In this paper, a new algorithm for technology mapping aiming standard-cell generators is proposed. The proposed method has features that explore several AND/OR circuit decompositions by using a n-ary tree representation of the circuit. In the covering step, the cell that leads to the smaller depth increase is chosen. Depth calculation is not limited to the subject tree and takes into account all previously mapped trees representing sub-expressions used as inputs. Experimental results show gains in circuit depth measured by the number of gates in series, as well as in area measured by transistor count when compared to SIS mapping approach using the same libraries. The gain in circuit depth translates to better timing as verified by spice simulations.

References

[1]
P. Abouzeid, R. Leveugle, G. Saucier, and R. Jamier, "Logic synthesis for automatic layout," in Proceedings of the Euro ASIC'92, pp. 146--151, 1992.
[2]
M. Berkelaar, J. Jess. "Technology mapping for standard-cell generators". IEEE ICCAD '88, Santa Clara, pp. 470--473, 1988.
[3]
E. Detjens, G. Gannot, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang, "Technology mapping in MIS," IEEE ICCAD '87, pp. 116--119, 1987.
[4]
ELIS Tool Home Page: http://www.inf.ufrgs.br/lagarto
[5]
K. Keutzer, "DAGON: technology binding and local optimization by DAG matching", 24th ACM/IEEE conference proceedings on Design automation conference, June 28-July 01, Miami Beach, Florida, United States, pp. 341--347, 1987.
[6]
Y. Kukimoto, R. K. Brayton, P. Sawkar, "Delay-optimal technology mapping by DAG covering", Proceedings of the 35th annual conference on Design automation conference, San Francisco, California, United States, pp. 348--351, June 1998.
[7]
E. Lehman, Y. Watanabe, J. Grodstein, H. Harkness, "Logic Decomposition During Technology Mapping". IEEE ICCAD '95, pp. 264 --271, November 1995.
[8]
F. Mailhot, G. DeMicheli - "Algorithms for technology mapping based on bynary decision diagrams and on Boolean operations", IEEE Transactions on CAD for IC and Systems, vol. 12 n° 5, pp. 599--620, 1993.
[9]
SIS: A System for Sequential Circuits Synthesis (Logic Synthesis Tool). University of California, Berkeley, 1992.
[10]
L. Stok, M. A. Iyer, A. J. Sullivan, "Wavefront technology mapping", Proceedings of the conference on Design, automation and test in Europe, Munich, Germany, pp.108--es, January 1999.
[11]
M. Zhao, S. S. Sapatnekar, "A new structural pattern matching algorithm for technology mapping". Proceedings of the 38th Conference on Design Automation, Publisher ACM Press, New York, NY, United States, pp. 371--376, June 2001.

Cited By

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  • (2019)Efficiently Mapping VLSI Circuits With Simple CellsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.281870938:4(692-704)Online publication date: Apr-2019
  • (2014)Deriving Reduced Transistor Count Circuits from AIGsProceedings of the 27th Symposium on Integrated Circuits and Systems Design10.1145/2660540.2661008(1-7)Online publication date: 1-Sep-2014
  • (2014)Optimization on cell-library design for digital Application Specific Printed Electronics Circuits2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2014.6951885(1-6)Online publication date: Sep-2014
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    cover image ACM Conferences
    SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design
    September 2004
    296 pages
    ISBN:1581139470
    DOI:10.1145/1016568
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 04 September 2004

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    Author Tags

    1. cell library
    2. complex gates
    3. library-free
    4. logic synthesis
    5. technology mapping

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    View all
    • (2019)Efficiently Mapping VLSI Circuits With Simple CellsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.281870938:4(692-704)Online publication date: Apr-2019
    • (2014)Deriving Reduced Transistor Count Circuits from AIGsProceedings of the 27th Symposium on Integrated Circuits and Systems Design10.1145/2660540.2661008(1-7)Online publication date: 1-Sep-2014
    • (2014)Optimization on cell-library design for digital Application Specific Printed Electronics Circuits2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2014.6951885(1-6)Online publication date: Sep-2014
    • (2013)Iterative remapping respecting timing constraints2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2013.6654639(236-241)Online publication date: Aug-2013
    • (2012)KL-cut based digital circuit remappingNORCHIP 201210.1109/NORCHP.2012.6403106(1-4)Online publication date: Nov-2012
    • (2012)Functional composition: A new paradigm for performing logic synthesisThirteenth International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2012.6187500(236-242)Online publication date: Mar-2012
    • (2009)Area minimization for library-free synthesis2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference10.1109/NEWCAS.2009.5290465(1-4)Online publication date: Jun-2009
    • (2008)Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering9th International Symposium on Quality Electronic Design (isqed 2008)10.1109/ISQED.2008.4479696(47-52)Online publication date: Mar-2008
    • (2008)Library-free synthesis for area-delay minimization2008 International Conference on Microelectronics10.1109/ICM.2008.5393800(187-191)Online publication date: Dec-2008

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