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Body-bias compensation technique for SubThreshold CMOS static logic gates

Published: 04 September 2004 Publication History

Abstract

This paper analyzes the performance of the conventional CMOS inverter, NAND-2 and NOR-2 static logic gates operating in the subthreshold region. The dependence of the drain currents on the process parameters can give rise to drive currents of NMOS and PMOS transistors that differ by an order of magnitude or even more. To compensate for this difference in currents, we propose three bias circuits in single-well processes that adjust the body voltage. Computer simulations using the AMS 0.8um technology and the BSIM3v3 model were carried out to assess the compensation technique. A test chip was fabricated in both AMIS 1.5um and TSMC0.35um to further validate the proposal.

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Cited By

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  • (2015)Selective Body Biasing for Post-Silicon Tuning of Sub-Threshold Designs: An Adaptive Filtering ApproachIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.240155234:5(713-725)Online publication date: May-2015
  • (2014)Ultra-low voltage CMOS logic circuits2014 Argentine Conference on Micro-Nanoelectronics, Technology and Applications (EAMTA)10.1109/EAMTA.2014.6906070(1-7)Online publication date: Jul-2014
  • (2013)Subthreshold Logic Using Body-Bias Technique for Digital VLSI Neural Applications2013 International Conference on Machine Intelligence and Research Advancement10.1109/ICMIRA.2013.66(316-320)Online publication date: Dec-2013
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  1. Body-bias compensation technique for SubThreshold CMOS static logic gates

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        cover image ACM Conferences
        SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design
        September 2004
        296 pages
        ISBN:1581139470
        DOI:10.1145/1016568
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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        Published: 04 September 2004

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        Author Tags

        1. CMOS
        2. body-bias compensation
        3. logic circuits
        4. low-power
        5. static logic
        6. subthreshold

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        View all
        • (2015)Selective Body Biasing for Post-Silicon Tuning of Sub-Threshold Designs: An Adaptive Filtering ApproachIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.240155234:5(713-725)Online publication date: May-2015
        • (2014)Ultra-low voltage CMOS logic circuits2014 Argentine Conference on Micro-Nanoelectronics, Technology and Applications (EAMTA)10.1109/EAMTA.2014.6906070(1-7)Online publication date: Jul-2014
        • (2013)Subthreshold Logic Using Body-Bias Technique for Digital VLSI Neural Applications2013 International Conference on Machine Intelligence and Research Advancement10.1109/ICMIRA.2013.66(316-320)Online publication date: Dec-2013
        • (2011)Subthreshold Schmitt trigger using body-bias technique for ultra low power and high performance applicationsRussian Microelectronics10.1134/S106373971006104640:2(141-145)Online publication date: 30-Mar-2011
        • (2010)Performance enhancement of subthreshold circuits using substrate biasing and charge-boosting buffersProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785566(369-372)Online publication date: 16-May-2010
        • (2010)Ultra low energy standard cell design optimization for performance and placement algorithmProceedings of the International Conference on Green Computing10.1109/GREENCOMP.2010.5598273(509-517)Online publication date: 15-Aug-2010
        • (2010)Digital Subthreshold for Ultra-Low Power Operation: Prospects and ChallengesLow-Power Variation-Tolerant Design in Nanometer Silicon10.1007/978-1-4419-7418-1_6(185-207)Online publication date: 25-Oct-2010
        • (2009)Device and circuit design challenges in the digital subthreshold region for ultralow-power applicationsVLSI Design10.1155/2009/2837022009(1-14)Online publication date: 1-Jan-2009
        • (2008)Oxide Thickness Optimization for Digital Subthreshold OperationIEEE Transactions on Electron Devices10.1109/TED.2007.91238355:2(685-688)Online publication date: Feb-2008
        • (2008)Variability-aware design of subthreshold devices2008 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2008.4541638(1196-1199)Online publication date: May-2008
        • Show More Cited By

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