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Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures

Published: 08 September 2004 Publication History

Abstract

State-of-the-art architecture description languages have been successfully used to model application-specific programmable architectures limited to particular control schemes. In this paper, we introduce a language and methodology that provide a framework for constructing and simulating a wider range of architectures. The framework exploits the fact that designers are often only concerned with data paths, not the instruction set and control. In the framework, each processing element is described in a structural language that only requires the specification of the data path and constraints on how it can be used. From such a description, the supported operations of the processing element are automatically extracted and a controller is generated. Various architectures are then realized by composing the processing elements. Furthermore, hardware descriptions and bit-true cycle-accurate simulators are automatically generated. Results show that our simulators are up to an order of magnitude faster than other reported simulators of this type and two orders of magnitude faster than equivalent Verilog simulations.

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Cited By

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  • (2010)Adaptive High-Speed Processor SimulationProcessor and System-on-Chip Simulation10.1007/978-1-4419-6175-4_9(145-159)Online publication date: 17-Aug-2010
  • (2009)Generating an Efficient Instruction Set Simulator from a Complete Property SuiteProceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping10.1109/RSP.2009.19(109-115)Online publication date: 23-Jun-2009
  • (2008)Fast cycle-approximate instruction set simulationProceedings of the 11th international workshop on Software & compilers for embedded systems10.1145/1361096.1361109(69-78)Online publication date: 13-Mar-2008

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cover image ACM Conferences
CODES+ISSS '04: Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
September 2004
266 pages
ISBN:158113 9373
DOI:10.1145/1016720
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 08 September 2004

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Author Tags

  1. automatic control generation
  2. cycle-accurate simulation
  3. instruction set extraction

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Cited By

View all
  • (2010)Adaptive High-Speed Processor SimulationProcessor and System-on-Chip Simulation10.1007/978-1-4419-6175-4_9(145-159)Online publication date: 17-Aug-2010
  • (2009)Generating an Efficient Instruction Set Simulator from a Complete Property SuiteProceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping10.1109/RSP.2009.19(109-115)Online publication date: 23-Jun-2009
  • (2008)Fast cycle-approximate instruction set simulationProceedings of the 11th international workshop on Software & compilers for embedded systems10.1145/1361096.1361109(69-78)Online publication date: 13-Mar-2008

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