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Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling

Authors:

Margaret Martonosi,

Sharad MalikAuthors Info & Claims

ACM Transactions on Architecture and Code Optimization (TACO), Volume 1, Issue 3

Pages 323 - 367

https://doi.org/10.1145/1022969.1022973

Published: 01 September 2004 Publication History

Abstract

Dynamic voltage scaling (DVS) has become an important dynamic power-management technique to save energy. DVS tunes the power-performance tradeoff to the needs of the application. The goal is to minimize energy consumption while meeting performance needs. Since CPU power consumption is strongly dependent on the supply voltage, DVS exploits the ability to control the power consumption by varying a processor's supply voltage and clock frequency. However, because of the energy and time overhead associated with switching DVS modes, DVS control has been used mainly at the interprogram level.In this paper, we explore the opportunities and limits of intraprogram DVS scheduling. An analytical model is derived to predict the maximum energy savings that can be obtained using intraprogram DVS given a few known program and processor parameters. This model gives insights into scenarios where energy consumption benefits from intraprogram DVS and those where there is no benefit. The model helps us extrapolate the benefits of intraprogram DVS into the future as processor parameters change. We then examine how much of these predicted benefits can actually be achieved through compile-time optimal settings of DVS modes. We extend an existing mixed-integer linear program formulation for this scheduling problem by accurately accounting for DVS energy switching overhead, by providing finer-grained control on settings and by considering multiple data categories in the optimization. Overall, this research provides a comprehensive view of intraprogram compile-time DVS management, providing both practical techniques for its immediate deployment as well theoretical bounds for use into the future.

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Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling

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cover image ACM Transactions on Architecture and Code Optimization

ACM Transactions on Architecture and Code Optimization Volume 1, Issue 3

September 2004

121 pages

ISSN:1544-3566

EISSN:1544-3973

DOI:10.1145/1022969

Issue’s Table of Contents

Copyright © 2004 ACM.

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Publication History

Published: 01 September 2004

Published in TACO Volume 1, Issue 3

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Yao YLu Z(2020)Pursuing Extreme Power Efficiency With PPCC Guided NoC DVFSIEEE Transactions on Computers10.1109/TC.2019.294980769:3(410-426)Online publication date: 1-Mar-2020
https://dl.acm.org/doi/10.1109/TC.2019.2949807
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https://doi.org/10.1016/bs.adcom.2015.04.001
Själander MMartonosi MKaxiras S(2014)Power-Efficient Computer Architectures: Recent AdvancesSynthesis Lectures on Computer Architecture10.2200/S00611ED1V01Y201411CAC0309:3(1-96)Online publication date: Dec-2014
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