skip to main content
10.1145/1023833.1023863acmconferencesArticle/Chapter ViewAbstractPublication PagesesweekConference Proceedingsconference-collections
Article

An efficient system-on-a-chip design methodology for networking applications

Published: 22 September 2004 Publication History

Abstract

This paper presents a System-on-a-Chip design methodology that uses a microprocessor subsystem as a building block for the development of chips for networking applications. The microprocessor subsystem is a self-contained macro that functions as an accelerator for computation-intensive pieces of the application code, and complements the standard components of the SoC. It consists of processor cores, memory banks, and well-defined interfaces that are interconnected via a high-performance switch. The number of processors and memory banks are parameters that can vary depending on the application to be implemented on the chip. Applications such as protocol conversion, TCP/IP off-load engine, or firewalls can be implemented with processor counts ranging from 8 to 128.

References

[1]
Georgiou, C.J., Salapura, V., Denneau, M. A Programmable Scalable Platform for Next Generation Networking. Network Processor Design, Issues and Practices, vol. 2, Chapter 2, Morgan Kaufmann Publishers, San Francisco, California, 2004, pp. 9--28
[2]
Brinkmann, A., Niemann, J.C., Hehemann, I., Langen, D., Porrmann, M., and Ruckert, U. On-Chip Interconnects for Next Generation System-on-Chips. In Proceedings of ASIC2003, Sept. 26-27, 2003, Rochester, New York.
[3]
Cesario, W.O., Lyonnard, D., Nicolescu, G., Paviot, Y., Yoo, S., Jerraya, A.A., Gauthier, L., Diaz-Nava, M. Multiprocessor SoC Platforms: A Component-Based Design Approach. IEEE Design and Test of Computers, Vol. 19, No. 6, November 2002, pp.52--63
[4]
IBM Corporation. CoreConnect bus architecture. http://www-3.ibm.com/chips/products coreconnect/
[5]
IBM Corporation. IBM introduces PowerPC 440 embedded processor. http://www-3.ibm.com/chips/news/__2003/ 0922_440ep.html
[6]
ARM. Processor Cores Overview. http://www.arm.com/ armtech/cpus?OpenDocument
[7]
MIPS. MIPS32 4KP - Embedded MIPS Processor Core. http://www.ce.chalmers.se/~thomasl/inlE/ mips32_4Kp_brief.pdf
[8]
Ryu, K.K., Shin, E., and Mooney, V.J. A Comparison of Five Different Multiprocessor SoC Bus Architectures. In Proceedings of the Euromicro Symposium on Digital System Design (DSS'01), Warsaw, Poland, September 2001.
[9]
Heddes, M. IBM Power Network processor architecture. In Proceedings of Hot Chips 12, Palo Alto, CA, USA, August 2000, IEEE Computer Society
[10]
NEC's New TCP/IP Offload Engine Powered by 10 Tensilica Xtensa Processor Cores. http://www.tensilica.com/ html/pr_2003_05_12.html
[11]
Wolf, T., and Franklin, M.A. Design Tradeoffs for Embedded Network Processors. In Proceedings of the International Conference on Architecture of Computing Systems (ARCS) (Lecture Notes in Computer Science), vol. 2299, pp. 149--164, Karlsruhe, Germany, April 2002. Springer Verlag
[12]
Internet Engineering Task Force. Small Computer Systems Interface protocol over the Internet (iSCSI) Requirements and Design Considerations. Request for Comments: 3347. ftp://ftp.rfc-editor.org/in-notes/ rfc3347.txt
[13]
Functional specification of SystemC 2.0. http://www.systemc.org/

Cited By

View all
  • (2007)Investigação do Uso de Caches com Suporte a Coerência de Dados em Plataformas MPSoC baseadas em NoCAnais do VIII Workshop em Sistemas Computacionais de Alto Desempenho (WSCAD 2007)10.5753/wscad.2007.18750(33-40)Online publication date: 24-Oct-2007
  • (2007)A time division multiplexing (TDM) logic mapping method for computational applicationsProceedings of the 2007 international conference on Computational science and its applications - Volume Part I10.5555/1802834.1802940(1096-1106)Online publication date: 26-Aug-2007
  • (2007)Cache coherency communication cost in a NoC-based MPSoC platformProceedings of the 20th annual conference on Integrated circuits and systems design10.1145/1284480.1284558(288-293)Online publication date: 3-Sep-2007
  • Show More Cited By

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences
CASES '04: Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
September 2004
324 pages
ISBN:1581138903
DOI:10.1145/1023833
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 September 2004

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. network processor
  2. system-on-a-chip

Qualifiers

  • Article

Conference

CASES04

Acceptance Rates

Overall Acceptance Rate 52 of 230 submissions, 23%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)0
  • Downloads (Last 6 weeks)0
Reflects downloads up to 16 Feb 2025

Other Metrics

Citations

Cited By

View all
  • (2007)Investigação do Uso de Caches com Suporte a Coerência de Dados em Plataformas MPSoC baseadas em NoCAnais do VIII Workshop em Sistemas Computacionais de Alto Desempenho (WSCAD 2007)10.5753/wscad.2007.18750(33-40)Online publication date: 24-Oct-2007
  • (2007)A time division multiplexing (TDM) logic mapping method for computational applicationsProceedings of the 2007 international conference on Computational science and its applications - Volume Part I10.5555/1802834.1802940(1096-1106)Online publication date: 26-Aug-2007
  • (2007)Cache coherency communication cost in a NoC-based MPSoC platformProceedings of the 20th annual conference on Integrated circuits and systems design10.1145/1284480.1284558(288-293)Online publication date: 3-Sep-2007
  • (2007)Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional BusesProceedings of the 2007 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2007.358072(720-725)Online publication date: 23-Jan-2007
  • (2007)A Time Division Multiplexing (TDM) Logic Mapping Method for Computational ApplicationsComputational Science and Its Applications – ICCSA 200710.1007/978-3-540-74472-6_91(1096-1106)Online publication date: 2007
  • (2006)On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC ArchitecturesProceedings of the 9th EUROMICRO Conference on Digital System Design10.1109/DSD.2006.73(53-60)Online publication date: 30-Aug-2006

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media