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Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems

Published: 22 September 2004 Publication History

Abstract

In embedded multithreaded architectures, the performance enhancement relative to the base single-threaded architecture is highly dependent on the characteristics of the application and memory configuration. When the application is well parallelized, the multithreading performance may be good even with a small cache since the memory access latency can be hidden. However, if there are complicated dependencies between threads, they cause frequent cache conflicts, so the performance may not be improved. For that reason, not only processor architecture but also memory configuration should be customized to get an optimal solution of an embedded multithreaded system. We suggest a design space exploration algorithm, which considers both memory configuration and multithreaded architecture and a thread shifting technique, which shifts threads in compile time to minimize cache conflict.

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Cited By

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  • (2006)Supporting microthread scheduling and synchronisation in CMPsInternational Journal of Parallel Programming10.1007/s10766-006-0017-y34:4(343-381)Online publication date: 1-Aug-2006

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  1. Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems

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        cover image ACM Conferences
        CASES '04: Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
        September 2004
        324 pages
        ISBN:1581138903
        DOI:10.1145/1023833
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        Published: 22 September 2004

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        Author Tags

        1. SMT
        2. design space exploration
        3. embedded systems
        4. simultaneous multithreading

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        • (2006)Supporting microthread scheduling and synchronisation in CMPsInternational Journal of Parallel Programming10.1007/s10766-006-0017-y34:4(343-381)Online publication date: 1-Aug-2006

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