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A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors

Published: 27 September 2003 Publication History

Abstract

Modern out-of-order processors tolerate long-latency memory operations by supporting a large number of in-flight instructions. This is achieved in part through proper sizing of critical resources, such as register files or instruction queues. In light of the increasing gap between processor speed and memory latency, tolerating upcoming latencies in this way would require impractical sizes of such critical resources.To tackle this scalability problem, we make a case for resource-conscious out-of-order processors. We present quantitative evidence that critical resources are increasingly underutilized in these processors. We advocate that better use of such resources should be a priority in future research in processor architectures. In particular, we present some of our research having such observations as a basis to deal with future resource conscious processors.

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Cited By

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  • (2008)Hiding the misprediction penalty of a resource-efficient high-performance processorACM Transactions on Architecture and Code Optimization10.1145/1328195.13282014:4(1-32)Online publication date: 30-Jan-2008
  • (2007)Implicit Transactional Memory in Kilo-Instruction MultiprocessorsAdvances in Computer Systems Architecture10.1007/978-3-540-74309-5_32(339-353)Online publication date: 2007
  • (2004)An analysis of a resource efficient checkpoint architectureACM Transactions on Architecture and Code Optimization10.1145/1044823.10448261:4(418-444)Online publication date: 1-Dec-2004
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Published In

cover image ACM Conferences
MEDEA '03: Proceedings of the 2003 workshop on MEmory performance: DEaling with Applications , systems and architecture
September 2003
75 pages
ISBN:9781450378208
DOI:10.1145/1152923
  • cover image ACM SIGARCH Computer Architecture News
    ACM SIGARCH Computer Architecture News  Volume 32, Issue 3
    Special issue: MEDEA-2003 workshop
    June 2004
    81 pages
    ISSN:0163-5964
    DOI:10.1145/1024295
    Issue’s Table of Contents
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Published: 27 September 2003

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Overall Acceptance Rate 6 of 9 submissions, 67%

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Cited By

View all
  • (2008)Hiding the misprediction penalty of a resource-efficient high-performance processorACM Transactions on Architecture and Code Optimization10.1145/1328195.13282014:4(1-32)Online publication date: 30-Jan-2008
  • (2007)Implicit Transactional Memory in Kilo-Instruction MultiprocessorsAdvances in Computer Systems Architecture10.1007/978-3-540-74309-5_32(339-353)Online publication date: 2007
  • (2004)An analysis of a resource efficient checkpoint architectureACM Transactions on Architecture and Code Optimization10.1145/1044823.10448261:4(418-444)Online publication date: 1-Dec-2004
  • (2004)Toward kilo-instruction processorsACM Transactions on Architecture and Code Optimization10.1145/1044823.10448251:4(389-417)Online publication date: 1-Dec-2004
  • (2004)Out-of-Order Commit ProcessorsProceedings of the 10th International Symposium on High Performance Computer Architecture10.1109/HPCA.2004.10008Online publication date: 14-Feb-2004
  • (2003)Kilo-instruction ProcessorsHigh Performance Computing10.1007/978-3-540-39707-6_2(10-25)Online publication date: 2003
  • (2007)A Flexible Heterogeneous Multi-Core Architecture16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)10.1109/PACT.2007.4336196(13-24)Online publication date: Sep-2007
  • (2006)A Decoupled KILO-Instruction ProcessorThe Twelfth International Symposium on High-Performance Computer Architecture, 2006.10.1109/HPCA.2006.1598112(52-63)Online publication date: 2006
  • (2004)Scalable Hardware Memory Disambiguation for High-ILP ProcessorsIEEE Micro10.1109/MM.2004.8724:6(118-127)Online publication date: 1-Nov-2004

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