article

Formal online methods for voltage/frequency control in multiple clock domain microprocessors

Authors:

Margaret Martonosi,

Douglas W. ClarkAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 32, Issue 5

Pages 248 - 259

https://doi.org/10.1145/1037947.1024423

Published: 07 October 2004 Publication History

Abstract

Multiple Clock Domain (MCD) processors are a promising future alternative to today's fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor has the extra flexibility to adjust the voltage and frequency in each domain independently. Most existing DVFS approaches are profile-based offline schemes which are mainly suitable for applications whose execution char-acteristics are constrained and repeatable. While some work has been published about online DVFS schemes, the prior approaches are typically heuristic-based. In this paper, we present an effective online DVFS scheme for an MCD processor which takes a formal analytic approach, is driven by dynamic workloads, and is suitable for all applications. In our approach, we model an MCD processor as a queue-domain network and the online DVFS as a feedback control problem with issue queue occupancies as feedback signals. A dynamic stochastic queuing model is first proposed and linearized through an accu-rate linearization technique. A controller is then designed and verified by stability analysis. Finally we evaluate our DVFS scheme through a cycle-accurate simulation with a broad set of applications selected from MediaBench and SPEC2000 benchmark suites. Compared to the best-known prior approach, which is heuristic-based, the proposed online DVFS scheme is substantially more effective due to its automatic regulation ability. For example, we have achieved a 2-3 fold increase in efficiency in terms of energy-delay product improvement. In addition, our control theoretic technique is more resilient, requires less tuning effort, and has better scalability as compared to prior online DVFS schemes.We believe that the techniques and methodology described in this paper can be generalized for energy control in processors other than MCD, such as tiled stream processors.

References

[1]

Carl Anderson. Tuning and optimization of a 170m transistor microprocessor. In Proceedings of the IEEE/ACM International Workshop on Timing Issue in the Specification and Synthesis of Digital System (TAU2000), Dec 2000.

[2]

K.J. Astrom and B. Wittenmark. Adaptive Control. Addison-Wesley, 1995.

Digital Library

[3]

S. K. Bose. An Introduction to Queueing Systems. Kluwer Academic, 2002.

[4]

D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimization. In Proc. of the ISCA-27, June 2000.

Digital Library

[5]

D. Burger and T. M. Austin. The SimpleScalar tool set version 2.0. Technical Report 97--1342, Department of Computer Science, University of Wisconsin-Madison, June 1997.

Digital Library

[6]

T. Chelcea and S. M. Nowick. Robust interfaces for mixed-timing systems with application to latency-insensitive protocols. In Proc. of DAC-2001, pages 21--26, 2001.

Digital Library

[7]

L.T. Clark. Circuit design of XScale microprocessors. In Proceedings of the 2001 Symposium on VLSI Circuits, June 2001.

[8]

M. Taylor et al. The RAW processor - a scalable 32-bit fabric for embedded and general purpose computing. In Proceedings of Hot Chips XIII, August 2001.

[9]

R.V. Hogg and A.T. Craig. Introduction to Mathematical Statistics, Fifth edition. Prentice Hall, 1995.

[10]

C-H Hsu and U. Kremer. The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction. In Proc. of PLDI-2003, pages 38--48, June 2003.

Digital Library

[11]

A. Iyer and D. Marculescu. Power efficiency of multiple clock multiple voltage cores. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 2002.

Digital Library

[12]

A. Iyer and D. Marculescu. Power-performance evaluation of globally asynchronous, locally synchronous processors. In Proc. of the 26th ISCA, May 2002.

Digital Library

[13]

K. Choi, R. Soma, and M. Pedram. Fine-grained dynamic voltage and frequency scaling for precise energy and performance trade-off based on the ratio of off-chip access to on-chip computation times. In Proceedings of DATE, Feb 2004.

Digital Library

[14]

B.C. Kuo. Automatic Control Systems., 7th edition. Prentice Hall, 1995.

Digital Library

[15]

D.V. Lindley. The theory of queues with a single server. In Proceedings of the Cambridge Philosophical Society, pages 277--289, 1952.

[16]

J. R. Lorch and A. J. Smith. Improving dynamic voltage scaling algorithm with PACE. In Proceedings of the SIGMETRICS-2001, pages 50--61, June 2001.

Digital Library

[17]

Z. Lu, J.Hein, M. Stan, J. Lach, and K. Skadron. Control-theoretic dynamic frequency and voltage scaling. In Proc. of the Intl. Conference on Compiler, Architecture, and Synchesis for Embedded Systems (CASES), October 2002.

Digital Library

[18]

G. Magklis, M.L. Scott, G. Semeraro, D.H. Albonesi, and S.Dropsho. Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor. In Proc. of the 30th ISCA, June 2003.

Digital Library

[19]

D. Marculescu. On the use of microarchitecture-driven dynamic voltage scaling. In In Workshop on Complexity Effective Design, Vancouver, Canada, June 2000., June 2000.

[20]

D. Marculescu, D.H. Albonesi, A. Buyuktosunoglu, and P. Bose. Partially asynchronous microprocessors (PAMs). In ISCA 2003 Tutorial, June 2003.

[21]

D. Matzke. Will physical scalability sabotage performance gains? IEEE Computer, pages 37--39, Sep 1997.

Digital Library

[22]

E. Perelman, G. Hamerly, and B. Calder. Picking statistically valid and early simulation points. In Proc. of the PACT-2003, September 2003.

Digital Library

[23]

G. Semeraro, D.H. Albonesi, S.G. Dropsho, G. Magklis, S. Dwarkadas, and M.L. Scott. Dynamic frequency and voltage control for a multiple clock domain microarchitecture. In Proc. of the 35th Micro, pages 356--367, November 2002.

Digital Library

[24]

G. Semeraro, G. Magklis, R. Balasubramonian, D.H. Albonesi, S. Dwarkadas, and M.L. Scott. Energy efficient processor design using multiple clock domains with dynamic voltage and frequency scaling. In Proc. of the 8th HPCA, pages 29--40, February 2002.

Digital Library

[25]

G. Semeraro, G. Magklis, and Y. Zhu. Personal communications. December 2003.

[26]

A.E. Sjogren and C.J. Myers. Interfacing synchronous and asynchronous modules within a high-speeed pipeline. In Proceedings of the 17th International Conference on Advanced Research in VLSI, pages 47--61, Sept 1997.

Digital Library

[27]

K. Skadron, T. Abdelzaher, and M. Stan. Control-theoretic techniques and thermal-rc modeling for accurate and localized dynamic thermal management. In Proc. of the 8th HPCA, February 2002.

Digital Library

[28]

Fen Xie, Margaret Martonosi, and Sharad Malik. Compile-time dynamic voltage scaling settings: Opportunities and limits. In Proc. of 2003 PLDI, June 2003.

Digital Library

[29]

K.Y. Yun and A. E. Dooply. Pausible clocking based heterogeneous systems. IEEE Transactions on VLSI Systems, 7(4):482--487, December 1999.

Digital Library

Cited By

Mishra NImes CLafferty JHoffmann H(2018)CALOREEACM SIGPLAN Notices10.1145/3296957.317318453:2(184-198)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3296957.3173184
Mishra NImes CLafferty JHoffmann HShen XTuck JBianchini RSarkar V(2018)CALOREEProceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3173162.3173184(184-198)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3173162.3173184
Pothukuchi RPothukuchi SVoulgaris PTorrellas J(2018)YuktaProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00049(505-518)Online publication date: 2-Jun-2018
https://dl.acm.org/doi/10.1109/ISCA.2018.00049
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Index Terms

Formal online methods for voltage/frequency control in multiple clock domain microprocessors
1. Computer systems organization
  1. Architectures
    1. Other architectures

Recommendations

Formal online methods for voltage/frequency control in multiple clock domain microprocessors
ASPLOS '04

Multiple Clock Domain (MCD) processors are a promising future alternative to today's fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor has the extra flexibility to adjust the voltage and frequency in each domain ...
Formal online methods for voltage/frequency control in multiple clock domain microprocessors
ASPLOS '04

Multiple Clock Domain (MCD) processors are a promising future alternative to today's fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor has the extra flexibility to adjust the voltage and frequency in each domain ...
Formal online methods for voltage/frequency control in multiple clock domain microprocessors
ASPLOS XI: Proceedings of the 11th international conference on Architectural support for programming languages and operating systems

Multiple Clock Domain (MCD) processors are a promising future alternative to today's fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor has the extra flexibility to adjust the voltage and frequency in each domain ...

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 32, Issue 5

ASPLOS 2004

December 2004

283 pages

ISSN:0163-5964

DOI:10.1145/1037947

Issue’s Table of Contents

ASPLOS XI: Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
October 2004
296 pages
ISBN:1581138040
DOI:10.1145/1024393
General Chair:
Shubu Mukherjee
Intel Corporation
,
Program Chair:
Kathryn S. McKinley
University of Texas at Austin

Copyright © 2004 ACM.

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Association for Computing Machinery

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Published: 07 October 2004

Published in SIGARCH Volume 32, Issue 5

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Cited By

Mishra NImes CLafferty JHoffmann H(2018)CALOREEACM SIGPLAN Notices10.1145/3296957.317318453:2(184-198)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3296957.3173184
Mishra NImes CLafferty JHoffmann HShen XTuck JBianchini RSarkar V(2018)CALOREEProceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3173162.3173184(184-198)Online publication date: 19-Mar-2018
https://dl.acm.org/doi/10.1145/3173162.3173184
Pothukuchi RPothukuchi SVoulgaris PTorrellas J(2018)YuktaProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00049(505-518)Online publication date: 2-Jun-2018
https://dl.acm.org/doi/10.1109/ISCA.2018.00049
Kunkel JDolz M(2018)Understanding hardware and software metrics with respect to power consumptionSustainable Computing: Informatics and Systems10.1016/j.suscom.2017.10.01617(43-54)Online publication date: Mar-2018
https://doi.org/10.1016/j.suscom.2017.10.016
Shahhosseini SMoazzemi KRahmani ADutt N(2018)On the feasibility of SISO control-theoretic DVFS for power capping in CMPsMicroprocessors and Microsystems10.1016/j.micpro.2018.09.01263(249-258)Online publication date: Nov-2018
https://doi.org/10.1016/j.micpro.2018.09.012
Shahosseini SMoazzemi KRahmani ADutt N(2017)Dependability evaluation of SISO control-theoretic power managers for processor architectures2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)10.1109/NORCHIP.2017.8124983(1-6)Online publication date: Oct-2017
https://doi.org/10.1109/NORCHIP.2017.8124983
Dutt NJantsch ASarma S(2016)Toward Smart Embedded SystemsACM Transactions on Embedded Computing Systems10.1145/287293615:2(1-27)Online publication date: 17-Feb-2016
https://dl.acm.org/doi/10.1145/2872936
Lari VLARI V(2016)Self-adaptive Power and Energy Management for TCPAsInvasive Tightly Coupled Processor Arrays10.1007/978-981-10-1058-3_3(83-113)Online publication date: 9-Jul-2016
https://doi.org/10.1007/978-981-10-1058-3_3
Tilli ABartolini ACacciari MBenini L(2015)Guaranteed Computational Resprinting via Model-Predictive ControlACM Transactions on Embedded Computing Systems10.1145/272471514:3(1-26)Online publication date: 21-Apr-2015
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Bailey PLowenthal DRavi VRountree BSchulz MSupinski B(2014)Adaptive Configuration Selection for Power-Constrained Heterogeneous SystemsProceedings of the 2014 Brazilian Conference on Intelligent Systems10.1109/ICPP.2014.46(371-380)Online publication date: 18-Oct-2014
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