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Reconfigurable hardware solutions for the digital rights management of digital cinema

Published: 25 October 2004 Publication History

Abstract

This paper presents a hardware implementation of a decoder for Digital Cinema images. This decoder enables us to deal with image size of 2K with 24 frames per second and 36 bits per pixels. It is the first implementation known nowadays that perfectly fits in one single Virtex-II® FPGA and includes AES decryption, JPEG 2000 decompression and fingerprinting blocks. This hardware offers therefore high-quality image processing as well as robust security.

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Cited By

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  • (2013)Hardware Implementations of Image/Video Watermarking AlgorithmsDigital Rights Management10.4018/978-1-4666-2136-7.ch010(148-176)Online publication date: 2013
  • (2010)Hardware Implementations of Image/Video Watermarking AlgorithmsAdvanced Techniques in Multimedia Watermarking10.4018/978-1-61520-903-3.ch017(425-454)Online publication date: 2010
  • (2005)FPGA-Based Content Protection System for Embedded Consumer ElectronicsProceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications10.1109/RTCSA.2005.55(502-507)Online publication date: 17-Aug-2005

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  1. Reconfigurable hardware solutions for the digital rights management of digital cinema

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    cover image ACM Conferences
    DRM '04: Proceedings of the 4th ACM workshop on Digital rights management
    October 2004
    120 pages
    ISBN:1581139691
    DOI:10.1145/1029146
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 25 October 2004

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    Author Tags

    1. AES
    2. DRM
    3. FPGA
    4. JPEG 2000
    5. digital cinema
    6. watermarking

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    View all
    • (2013)Hardware Implementations of Image/Video Watermarking AlgorithmsDigital Rights Management10.4018/978-1-4666-2136-7.ch010(148-176)Online publication date: 2013
    • (2010)Hardware Implementations of Image/Video Watermarking AlgorithmsAdvanced Techniques in Multimedia Watermarking10.4018/978-1-61520-903-3.ch017(425-454)Online publication date: 2010
    • (2005)FPGA-Based Content Protection System for Embedded Consumer ElectronicsProceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications10.1109/RTCSA.2005.55(502-507)Online publication date: 17-Aug-2005

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