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Techniques for synthesizing binaries to an advanced register/memory structure

Published: 20 February 2005 Publication History

Abstract

Recent works demonstrate several benefits of synthesizing software binaries onto FPGA hardware, including incorporating hardware design into established software tool flows with minimal impact, porting existing binaries to FPGAs, and even dynamically synthesizing software kernels to faster FPGA coprocessors. Those works showed that standard binary decompilation methods can recover enough high-level control information to result in reasonably-efficient hardware. However, recent synthesis methods for FPGAs utilize advanced memory structures, such as a "smart buffer," that require recovery of additional high-level information, specifically information about loops and arrays. We incorporate decompilation techniques into an existing binary synthesis tool flow to recover loops and arrays in order to take advantage of advanced memory structures when performing synthesis from a binary. We demonstrate through experiments on six benchmarks that our methods improve binary synthesis performance by 53%, by making effective use of smart buffers. Furthermore, we compare the binary results using smart buffers with results of synthesis directly from the original C code for the benchmarks, and show that our methods achieved almost identical performance results with only 10% area overhead.

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Cited By

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  • (2017)Synthesis of program binaries into FPGA accelerators with runtime dependence validation2017 International Conference on Field Programmable Technology (ICFPT)10.1109/FPT.2017.8280126(96-103)Online publication date: Dec-2017
  • (2013)Using memory profile analysis for automatic synthesis of pointers codeACM Transactions on Embedded Computing Systems10.1145/2442116.244211812:3(1-21)Online publication date: 8-Apr-2013
  • (2012)Improving Security Assurance of Embedded Systems through Systemic Dissolution of Architected ResourcesProceedings of the 2012 45th Hawaii International Conference on System Sciences10.1109/HICSS.2012.318(5384-5392)Online publication date: 4-Jan-2012
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      cover image ACM Conferences
      FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
      February 2005
      288 pages
      ISBN:1595930299
      DOI:10.1145/1046192
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 20 February 2005

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      Author Tags

      1. FPGA
      2. binaries
      3. decompilation
      4. embedded systems
      5. smart buffers
      6. synthesis

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      View all
      • (2017)Synthesis of program binaries into FPGA accelerators with runtime dependence validation2017 International Conference on Field Programmable Technology (ICFPT)10.1109/FPT.2017.8280126(96-103)Online publication date: Dec-2017
      • (2013)Using memory profile analysis for automatic synthesis of pointers codeACM Transactions on Embedded Computing Systems10.1145/2442116.244211812:3(1-21)Online publication date: 8-Apr-2013
      • (2012)Improving Security Assurance of Embedded Systems through Systemic Dissolution of Architected ResourcesProceedings of the 2012 45th Hawaii International Conference on System Sciences10.1109/HICSS.2012.318(5384-5392)Online publication date: 4-Jan-2012
      • (2011)Thread WarpingACM Transactions on Design Automation of Electronic Systems10.1145/1970353.197036516:3(1-21)Online publication date: 1-Jun-2011
      • (2011)Increasing computational density of application-specific systems2011 Electronic System Level Synthesis Conference (ESLsyn)10.1109/ESLsyn.2011.5952293(1-6)Online publication date: Jun-2011
      • (2011)Synthesizing Concurrent Synchronous Computing Machines from Interrupt-Driven BinariesProceedings of the 2011 14th Euromicro Conference on Digital System Design10.1109/DSD.2011.59(430-433)Online publication date: 31-Aug-2011
      • (2011)Combining static and dynamic array detection for binary synthesis with multiple memory portsDesign Automation for Embedded Systems10.1007/s10617-010-9065-z15:1(1-18)Online publication date: 1-Mar-2011
      • (2010)Automatic memory partitioningProceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/1878961.1878989(155-162)Online publication date: 24-Oct-2010
      • (2009)Automatic Reconfigurable System-on-Chip design with run-time hardware/software partitioning2009 11th IEEE International Conference on Computer-Aided Design and Computer Graphics10.1109/CADCG.2009.5246854(484-491)Online publication date: Aug-2009
      • (2008)Binary synthesisACM Transactions on Design Automation of Electronic Systems10.1145/1255456.125547112:3(1-30)Online publication date: 22-May-2008
      • Show More Cited By

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