Article

Multilevel full-chip routing with testability and yield enhancement

Authors:

Katherine Shu-Min Li,

Chung-Len Lee,

Yao-Wen Chang,

Chauchin Su,

Jwu-E ChenAuthors Info & Claims

SLIP '05: Proceedings of the 2005 international workshop on System level interconnect prediction

Pages 29 - 36

https://doi.org/10.1145/1053355.1053362

Published: 02 April 2005 Publication History

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Abstract

We propose a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two major issues are addressed. (1) The oscillation ring (OR) test and its diagnosis scheme for interconnect based on the IEEE P1500 are integrated into the multilevel routing framework to achieve testability enhancement. (2) We present a heuristic to balance routing congestion to optimize the multiple-fault probability, chemical mechanic polishing (CMP) and optical proximity correction (OPC) induced manufacturability, and crosstalk effects, for yield improvement. Experimental results on the MCNC benchmark circuits show that the proposed OR method achieves 100% fault coverage and the maximal diagnosis resolution for interconnects, and the multilevel routing algorithm effectively balances the routing density to achieve 100% routing completion. Compared with [14], the experimental results show that our router improves the maximal congestion by 1.24X--6.11X in runtime speedup by 1.08X--7.66X, and improves the average congestion by 1.00X--4.52X with the improved congestion deviation by 1.37X--5.55X.

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Cited By

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Wei YSapatnekar SSaxena PChang Y(2010)Dummy fill optimization for enhanced manufacturabilityProceedings of the 19th international symposium on Physical design10.1145/1735023.1735051(97-104)Online publication date: 14-Mar-2010
https://dl.acm.org/doi/10.1145/1735023.1735051
Lin CTsai MLee KChen TWang TChang Y(2007)Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability2007 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2007.357992(238-243)Online publication date: Jan-2007
https://doi.org/10.1109/ASPDAC.2007.357992
Chang YChen TChen H(2007)Physical Design for System-On-A-ChipEssential Issues in SOC Design10.1007/1-4020-5352-5_9(311-403)Online publication date: 2007
https://doi.org/10.1007/1-4020-5352-5_9

Index Terms

Multilevel full-chip routing with testability and yield enhancement
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

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Published In

SLIP '05: Proceedings of the 2005 international workshop on System level interconnect prediction

April 2005

114 pages

ISBN:1595930337

DOI:10.1145/1053355

General Chair:
Igor Markov
University of Michigan, USA
,
Program Chair:
Mike Hutton
Altera, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 02 April 2005

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SLIP05: International Workshop on System Level Interconnect Prediction

April 2 - 3, 2005

California, San Francisco, USA

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Overall Acceptance Rate 6 of 8 submissions, 75%

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Wei YSapatnekar SSaxena PChang Y(2010)Dummy fill optimization for enhanced manufacturabilityProceedings of the 19th international symposium on Physical design10.1145/1735023.1735051(97-104)Online publication date: 14-Mar-2010
https://dl.acm.org/doi/10.1145/1735023.1735051
Lin CTsai MLee KChen TWang TChang Y(2007)Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability2007 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2007.357992(238-243)Online publication date: Jan-2007
https://doi.org/10.1109/ASPDAC.2007.357992
Chang YChen TChen H(2007)Physical Design for System-On-A-ChipEssential Issues in SOC Design10.1007/1-4020-5352-5_9(311-403)Online publication date: 2007
https://doi.org/10.1007/1-4020-5352-5_9

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