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Power-performance simulation: design and validation strategies

Authors:

David Brooks,

Pradip Bose,

Margaret MartonosiAuthors Info & Claims

ACM SIGMETRICS Performance Evaluation Review, Volume 31, Issue 4

Pages 13 - 18

https://doi.org/10.1145/1054907.1054911

Published: 01 March 2004 Publication History

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Abstract

Microprocessor research and development increasingly relies on detailed simulations to make design choices. As such, the structure, speed, and accuracy of microarchitectural simulators is of critical importance to the field. This paper describes our experiences in building two simulators, using related but distinct approaches.One of the most important attributes of a simulator is its ability to accurately convey design trends as different aspects of the microarchitecture are varied. In this work, we break down accuracy---a broad term--- into two sub-types: relative and absolute accuracy. We then discuss typical abstraction errors in power-performance simulators and show when they do (or do not) affect the design rule choices a user of those simulator might make. By performing this validation study using the Wattch and Power Timer simulators, the work addresses validation issues both broadly and in the specific case of a fairly widely-used simulator.

References

[1]

B. Amrutur and M. Horowitz, Speed and power scaling of SRAM's. IEEE Journal of Solid-State Circuits, 35(2):175--185, 2000.]]

Crossref

Google Scholar

[2]

D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In Proceedings of the 27th Annual International Symposium on Computer Architecture, June 2000.]]

Digital Library

Google Scholar

[3]

D. Brooks, J.-D. Wellman, P. Bose, and M. Martonosi. Power-Performance Modeling and Tradeoff Analysis for a High-End Microprocessor. In Power Aware Computing Systems Workshop at ASPLOS-IX, Nov. 2000.]]

Digital Library

Google Scholar

[4]

M. Moudgill, P. Bose, and J. Moreno. Validation of Turandot, a fast processor model for microarchitecture exploration. In Proceedings of the IEEE International Performance, Computing, and Communications Conference (IPCCC), pages 451--457, Feb. 1999.]]

Crossref

Google Scholar

[5]

M. Moudgill, J. Wellman, and J. Moreno. Environment for PowerPC microarchitecture exploration. IEEE Micro, 19(3):9--14, May/June 1999.]]

Digital Library

Google Scholar

[6]

G. Reinman and N. Jouppi. CACTI 2.0: An Integrated Cache Timing and Power Model. In WRL Research Report 2000/7, 2000.]]

Google Scholar

[7]

N. Vijaykrishnan, M. Kandemir, M. Irwin, H. Kim, and W. Ye. Energy-driven integrated hardware-software optimizations using simple-power. In Proceedings of the 27th Annual International Symposium on Computer Architecture, June 2000.]]

Digital Library

Google Scholar

[8]

S. Wilton and N. Jouppi. An Enhanced Access and Cycle Time Model for On-chip Caches. In WRL Research Report 93/5, DEC Western Research Laboratory, 1994.]]

Google Scholar

[9]

V. Zyuban, Inherently Lower Power High Performance Superscalar Architectures. PhD thesis, University of Notre Dame, March 2000.]]

Digital Library

Google Scholar

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Vega ABose PBuyuktosunoglu ADeMara R(2017)Reliable and power-aware architecturesRugged Embedded Systems10.1016/B978-0-12-802459-1.00002-6(9-37)Online publication date: 2017
https://doi.org/10.1016/B978-0-12-802459-1.00002-6
Xi SJacobson HBose PWei GBrooks D(2015)Quantifying sources of error in McPAT and potential impacts on architectural studies2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2015.7056064(577-589)Online publication date: Feb-2015
https://doi.org/10.1109/HPCA.2015.7056064
Kornaros GPnevmatikatos D(2014)Dynamic Power and Thermal Management of NoC-Based Heterogeneous MPSoCsACM Transactions on Reconfigurable Technology and Systems10.1145/25676587:1(1-26)Online publication date: 1-Feb-2014
https://dl.acm.org/doi/10.1145/2567658
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cover image ACM SIGMETRICS Performance Evaluation Review

ACM SIGMETRICS Performance Evaluation Review Volume 31, Issue 4

Special issue on tools for computer architecture research

March 2004

34 pages

ISSN:0163-5999

DOI:10.1145/1054907

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Association for Computing Machinery

New York, NY, United States

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Published: 01 March 2004

Published in SIGMETRICS Volume 31, Issue 4

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Vega ABose PBuyuktosunoglu ADeMara R(2017)Reliable and power-aware architecturesRugged Embedded Systems10.1016/B978-0-12-802459-1.00002-6(9-37)Online publication date: 2017
https://doi.org/10.1016/B978-0-12-802459-1.00002-6
Xi SJacobson HBose PWei GBrooks D(2015)Quantifying sources of error in McPAT and potential impacts on architectural studies2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2015.7056064(577-589)Online publication date: Feb-2015
https://doi.org/10.1109/HPCA.2015.7056064
Kornaros GPnevmatikatos D(2014)Dynamic Power and Thermal Management of NoC-Based Heterogeneous MPSoCsACM Transactions on Reconfigurable Technology and Systems10.1145/25676587:1(1-26)Online publication date: 1-Feb-2014
https://dl.acm.org/doi/10.1145/2567658
Chakraborty SDeb DBuragohain DKapoor H(2014)Cache capacity and its effects on power consumption for tiled chip multi-processors2014 International Conference on Electronics and Communication Systems (ICECS)10.1109/ECS.2014.6892719(1-6)Online publication date: Feb-2014
https://doi.org/10.1109/ECS.2014.6892719
Jacobson HBuyuktosunoglu ABose PAcar EEickemeyer R(2011)Abstraction and microarchitecture scaling in early-stage power modeling2011 IEEE 17th International Symposium on High Performance Computer Architecture10.1109/HPCA.2011.5749746(394-405)Online publication date: Feb-2011
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Merentitis AKaloxylos AStamatelatos MAlonistioti N(2010)Optimal periodic radio sensing and low energy reasoning for cognitive devicesMelecon 2010 - 2010 15th IEEE Mediterranean Electrotechnical Conference10.1109/MELCON.2010.5476231(470-475)Online publication date: Apr-2010
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Merentitis AMargaris DKranitis NPaschalis AGizopoulos D(2010)SBST for on-line detection of hard faults in multiprocessor applications under energy constraintsProceedings of the 2010 IEEE 16th International On-Line Testing Symposium10.1109/IOLTS.2010.5560233(62-67)Online publication date: 5-Jul-2010
https://dl.acm.org/doi/10.1109/IOLTS.2010.5560233
Stralen PPimentel A(2010)A High-level Microprocessor Power Modeling Technique Based on Event SignaturesJournal of Signal Processing Systems10.1007/s11265-008-0301-860:2(239-250)Online publication date: 1-Aug-2010
https://dl.acm.org/doi/10.1007/s11265-008-0301-8
Merentitis AKranitis NPaschalis AGizopoulos D(2007)Selecting Power-Optimal SBST Routines for On-Line Processor TestingProceedings of the 12th IEEE European Test Symposium10.1109/ETS.2007.36(111-116)Online publication date: 20-May-2007
https://dl.acm.org/doi/10.1109/ETS.2007.36
Senn ELaurent JJulien NMartin E(2005)SoftexplorerEURASIP Journal on Advances in Signal Processing10.1155/ASP.2005.26412005(2641-2654)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.1155/ASP.2005.2641

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A probabilistic performance model for scalable simulation systems

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