Article

On-chip power distribution grids with multiple supply voltages for high performance integrated circuits

Authors:

Mikhail Popovich,

Eby G. Friedman,

Michael Sotman,

Avinoam KolodnyAuthors Info & Claims

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

Pages 2 - 7

https://doi.org/10.1145/1057661.1057665

Published: 17 April 2005 Publication History

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Abstract

Multiple supply voltages are often utilized to decrease power dissipation in high performance integrated circuits. On-chip power distribution grids with multiple supply voltages are discussed in this paper. A power distribution grid with multiple supply voltages and multiple grounds is presented. The proposed power delivery scheme reduces power supply voltage drops as compared to conventional power distribution systems with dual supplies and a single ground by 17% on average (20% maximum). For an example power grid with decoupling capacitors placed between the power supply and ground, the proposed grid with multiple supply and multiple ground exhibits, respectively, 13% and 18% average performance improvement. The proposed power distribution grid can be an alternative to a single supply voltage and single ground power distribution system.

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Cited By

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P.-Vaisband IJakushokas RPopovich MMezhiba AKöse SFriedman EVaisband IJakushokas RPopovich MMezhiba AKöse SFriedman E(2016)On-Chip Power Grids with Multiple Supply VoltagesOn-Chip Power Delivery and Management10.1007/978-3-319-29395-0_41(619-650)Online publication date: 27-Apr-2016
https://doi.org/10.1007/978-3-319-29395-0_41
Siu WMak T(2014)Intra- and inter-chip voltage droop analysis using a power delivery grid model2014 International Symposium on Integrated Circuits (ISIC)10.1109/ISICIR.2014.7029549(208-211)Online publication date: Dec-2014
https://doi.org/10.1109/ISICIR.2014.7029549
Zhou QShi JLiu BCai Y(2011)Floorplanning considering IR drop in multiple supply voltages island designsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.203742819:4(638-646)Online publication date: 1-Apr-2011
https://dl.acm.org/doi/10.1109/TVLSI.2009.2037428
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Index Terms

On-chip power distribution grids with multiple supply voltages for high performance integrated circuits
1. Hardware
  1. Integrated circuits

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Maximum effective distance of on-chip decoupling capacitors in power distribution grids
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Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the available white space on a die. The efficacy of on-chip decoupling capacitors depends upon the impedance of the ...

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Published In

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

April 2005

518 pages

ISBN:1595930574

DOI:10.1145/1057661

General Chair:
John Lach
University of Virginia
,
Program Chairs:
Gang Qu
University of Maryland, College Park
,
Yehea Ismail
Northwestern University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 April 2005

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GLSVLSI05: Great Lakes Symposium on VLSI 2005

April 17 - 19, 2005

Illinois, Chicago, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

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P.-Vaisband IJakushokas RPopovich MMezhiba AKöse SFriedman EVaisband IJakushokas RPopovich MMezhiba AKöse SFriedman E(2016)On-Chip Power Grids with Multiple Supply VoltagesOn-Chip Power Delivery and Management10.1007/978-3-319-29395-0_41(619-650)Online publication date: 27-Apr-2016
https://doi.org/10.1007/978-3-319-29395-0_41
Siu WMak T(2014)Intra- and inter-chip voltage droop analysis using a power delivery grid model2014 International Symposium on Integrated Circuits (ISIC)10.1109/ISICIR.2014.7029549(208-211)Online publication date: Dec-2014
https://doi.org/10.1109/ISICIR.2014.7029549
Zhou QShi JLiu BCai Y(2011)Floorplanning considering IR drop in multiple supply voltages island designsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.203742819:4(638-646)Online publication date: 1-Apr-2011
https://dl.acm.org/doi/10.1109/TVLSI.2009.2037428
Ding HWei Wang Zhiliang Qian Tsui CLai L(2011)Thermal modeling of three-dimensional integrated circuits considering the thermal removal capability of different TSVs2011 3rd Asia Symposium on Quality Electronic Design (ASQED)10.1109/ASQED.2011.6111693(1-7)Online publication date: Jul-2011
https://doi.org/10.1109/ASQED.2011.6111693
Ghosh PSen ADe Micheli GAl-Hashimi BMueller WMacii E(2010)Power efficient voltage islanding for Systems-on-Chip from a floorplanning perspectiveProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871081(654-657)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871081
Ghosh PSen A(2010)Energy efficient mapping and voltage islanding for regular NoC under design constraintsInternational Journal of High Performance Systems Architecture10.1504/IJHPSA.2010.0345352:3/4(132-144)Online publication date: 1-Aug-2010
https://dl.acm.org/doi/10.1504/IJHPSA.2010.034535
Ghosh PSen AShin SOssowski SSchumacher MPalakal MHung C(2010)Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraintsProceedings of the 2010 ACM Symposium on Applied Computing10.1145/1774088.1774197(535-541)Online publication date: 22-Mar-2010
https://dl.acm.org/doi/10.1145/1774088.1774197
Ghosh PSen A(2010)Power efficient voltage islanding for Systems-on-chip from a floorplanning perspective2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)10.1109/DATE.2010.5457124(654-657)Online publication date: Mar-2010
https://doi.org/10.1109/DATE.2010.5457124
Mishra PMuttreja AJha N(2009)Low-power FinFET circuit synthesis using multiple supply and threshold voltagesACM Journal on Emerging Technologies in Computing Systems10.1145/1543438.15434405:2(1-23)Online publication date: 16-Jul-2009
https://dl.acm.org/doi/10.1145/1543438.1543440
Chang MYang S(2009)Analysis and reduction of supply noise fluctuations induced by embedded via-programming ROMIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200679417:6(758-769)Online publication date: 1-Jun-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2006794
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