Low power test generation for path delay faults using stability functions
Pages 8 - 12
Abstract
A recent work describes an ATPG for path delay faults that limits the power dissipated by the test patterns to a given bound. However, the power dissipated by the intermediate patterns while applying the test patterns in a sequence is not considered. Experiments with test patterns derived from different ATPGs has shown that the switching activity due to intermediate patterns dissipate considerable power. This paper proposes a method to incorporate stability functions in a functional ATPG to derive test vectors that guarantee reduced power dissipation by the intermediate patterns without loss in PDF coverage.
References
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Index Terms
- Low power test generation for path delay faults using stability functions
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Published: 17 April 2005
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