Article

Thermal aware cell-based full-chip electromigration reliability analysis

Authors:

Donald E. Troxel,

Carl V. ThompsonAuthors Info & Claims

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

Pages 26 - 31

https://doi.org/10.1145/1057661.1057670

Published: 17 April 2005 Publication History

Abstract

A hierarchical scheme with cells and modules is crucial for managing design complexity during a large integrated circuit design. We present a methodology for thermal aware cell-based electromigration analysis suitable for integrating electromigration reliability analysis into a conventional IC design flow. A block or cell is characterized for reliability while it is characterized for power and timing. Reusing cell characterization data significantly reduces computational load while analyzing a full-chip layout. During full-chip analysis, we compute a layout-level temperature profile from cell power dissipations using a Fast Fourier Transform based algorithm. The described full-chip reliability assessment methodology has been implemented in an interconnect reliability CAD tool. We have exercised the tool to demonstrate performance-reliability tradeoff and the significance of thermal-aware reliability analysis for true reliability aware design.

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Cited By

Saraswat GAu WHe QVenkateswaran S(2017)FIT rate aware EM analysis2017 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI)10.1109/ISEMC.2017.8077974(786-790)Online publication date: Aug-2017
https://doi.org/10.1109/ISEMC.2017.8077974
Yao MZhang XZhao CMa J(2011)Self-consistent design issues for high frequency Cu interconnect reliability incorporating skin effectMicroelectronics Reliability10.1016/j.microrel.2010.12.01151:5(1003-1010)Online publication date: May-2011
https://doi.org/10.1016/j.microrel.2010.12.011
Helms DHylla KNebel WHenkel JKeshavarzi AChang NGhani T(2009)Hybrid logical-statistical simulation with thermal and IR-drop mapping for degradation and variation predictionProceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design10.1145/1594233.1594243(33-38)Online publication date: 19-Aug-2009
https://dl.acm.org/doi/10.1145/1594233.1594243
Show More Cited By

Index Terms

Thermal aware cell-based full-chip electromigration reliability analysis
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware

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Published In

cover image ACM Conferences

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

April 2005

518 pages

ISBN:1595930574

DOI:10.1145/1057661

General Chair:
John Lach
University of Virginia
,
Program Chairs:
Gang Qu
University of Maryland, College Park
,
Yehea Ismail
Northwestern University

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 17 April 2005

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GLSVLSI05: Great Lakes Symposium on VLSI 2005

April 17 - 19, 2005

Illinois, Chicago, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Saraswat GAu WHe QVenkateswaran S(2017)FIT rate aware EM analysis2017 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI)10.1109/ISEMC.2017.8077974(786-790)Online publication date: Aug-2017
https://doi.org/10.1109/ISEMC.2017.8077974
Yao MZhang XZhao CMa J(2011)Self-consistent design issues for high frequency Cu interconnect reliability incorporating skin effectMicroelectronics Reliability10.1016/j.microrel.2010.12.01151:5(1003-1010)Online publication date: May-2011
https://doi.org/10.1016/j.microrel.2010.12.011
Helms DHylla KNebel WHenkel JKeshavarzi AChang NGhani T(2009)Hybrid logical-statistical simulation with thermal and IR-drop mapping for degradation and variation predictionProceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design10.1145/1594233.1594243(33-38)Online publication date: 19-Aug-2009
https://dl.acm.org/doi/10.1145/1594233.1594243
Alam SGan CThompson CTroxel D(2007)Reliability computer-aided design tool for full-chip electromigration analysis and comparison with different interconnect metallizationsMicroelectronics Journal10.1016/j.mejo.2006.11.01738:4-5(463-473)Online publication date: Apr-2007
https://doi.org/10.1016/j.mejo.2006.11.017

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