We propose an energy-efficient architecture for instruction caches that relies on dynamic zero compression (DZC), that is, the possibility of reading and writing a single bit for every zero-valued byte [5]. We enhance the basic DZC by using a simple bit permutation to increase the number of zero-valued bytes, so that the corresponding overhead is negligible. The derivation of an effective permutation relies on a heuristic zero clustering algorithm that is based on the knowledge of the memory reference access trace, thus making this solution suitable for application-specific embedded systems. The architecture proposed in this work makes possible the application of zero compression to instruction caches; experiments showed an increase of zero clusters of more than 70% on average, which translates into a 10% improvement in dynamic energy savings with respect to DZC.