Article

A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology

Authors:

Alireza Hodjat,

David D. Hwang,

Ingrid VerbauwhedeAuthors Info & Claims

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

Pages 60 - 63

https://doi.org/10.1145/1057661.1057677

Published: 17 April 2005 Publication History

Abstract

In this paper an AES crypto coprocessor that is fabricated using a 0.18-μm CMOS technology is presented. This crypto coprocessor performs the AES-128 encryption in both feedback and non-feedback modes of operation. A maximum throughput of 3.84 Gbits/s is achieved at a 330 MHz clock frequency for ECB, OFB, and CBC modes of operation. This crypto coprocessor can be programmed using the memory-mapped interface of an embedded CPU core and is tested using a LEON 32-bit (SPARC V8) processor in the ThumbPod secure system-on-chip.

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Cited By

Wang PGuan WLiang L(2024)Design of a Low-Power Cryptographic Accelerator Under Advanced Encryption StandardJournal of Circuits, Systems and Computers10.1142/S021812662450305533:17Online publication date: 25-Jul-2024
https://doi.org/10.1142/S0218126624503055
Singha TPalathinkal RAhamed S(2023)Securing AES Designs Against Power Analysis Attacks: A SurveyIEEE Internet of Things Journal10.1109/JIOT.2023.326568310:16(14332-14356)Online publication date: 15-Aug-2023
https://doi.org/10.1109/JIOT.2023.3265683
Serrano RSarmiento MDuran CHoang TPham C(2022)A 3.65 Gb/s Area-Efficiency ChaCha20 Cryptocore2022 19th International SoC Design Conference (ISOCC)10.1109/ISOCC56007.2022.10031398(79-80)Online publication date: 19-Oct-2022
https://doi.org/10.1109/ISOCC56007.2022.10031398
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Index Terms

A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology
1. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific processors

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Published In

cover image ACM Conferences

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

April 2005

518 pages

ISBN:1595930574

DOI:10.1145/1057661

General Chair:
John Lach
University of Virginia
,
Program Chairs:
Gang Qu
University of Maryland, College Park
,
Yehea Ismail
Northwestern University

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 17 April 2005

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GLSVLSI05

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GLSVLSI05: Great Lakes Symposium on VLSI 2005

April 17 - 19, 2005

Illinois, Chicago, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Wang PGuan WLiang L(2024)Design of a Low-Power Cryptographic Accelerator Under Advanced Encryption StandardJournal of Circuits, Systems and Computers10.1142/S021812662450305533:17Online publication date: 25-Jul-2024
https://doi.org/10.1142/S0218126624503055
Singha TPalathinkal RAhamed S(2023)Securing AES Designs Against Power Analysis Attacks: A SurveyIEEE Internet of Things Journal10.1109/JIOT.2023.326568310:16(14332-14356)Online publication date: 15-Aug-2023
https://doi.org/10.1109/JIOT.2023.3265683
Serrano RSarmiento MDuran CHoang TPham C(2022)A 3.65 Gb/s Area-Efficiency ChaCha20 Cryptocore2022 19th International SoC Design Conference (ISOCC)10.1109/ISOCC56007.2022.10031398(79-80)Online publication date: 19-Oct-2022
https://doi.org/10.1109/ISOCC56007.2022.10031398
Jayasinghe DIgnjatovic ARagel RAmbrose JParameswaran S(2021)QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection AttacksACM Transactions on Design Automation of Electronic Systems10.1145/344370626:5(1-36)Online publication date: 5-Jun-2021
https://dl.acm.org/doi/10.1145/3443706
Mohan GM M(2021)High Throughput Folded Architecture of AES2021 5th Conference on Information and Communication Technology (CICT)10.1109/CICT53865.2020.9672409(1-6)Online publication date: 10-Dec-2021
https://doi.org/10.1109/CICT53865.2020.9672409
El-Moursy ADarya AElwakil AJha AMajzoub S(2020)Chaotic Clock Driven Cryptographic Chip: Towards a DPA Resistant AES ProcessorIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2020.3045802(1-1)Online publication date: 2020
https://doi.org/10.1109/TETC.2020.3045802
Jayasinghe DIgnjatovic AParameswaran S(2019)RFTCProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317899(1-6)Online publication date: 2-Jun-2019
https://dl.acm.org/doi/10.1145/3316781.3317899
HA QNGUYEN THA DLE M(2019)High Performance and Security Design for Cryptosystem Using Simultaneous Multiple Hardware Threads and Power Aware Technique2019 International Conference on System Science and Engineering (ICSSE)10.1109/ICSSE.2019.8823107(302-307)Online publication date: Jul-2019
https://doi.org/10.1109/ICSSE.2019.8823107
Evtyushkin DElwell JOzsoy MPonomarev DGhazaleh NRiley R(2018)Flexible Hardware-Managed Isolated Execution: Architecture, Software Support and ApplicationsIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2016.259628715:3(437-451)Online publication date: 1-May-2018
https://doi.org/10.1109/TDSC.2016.2596287
Basiri M MShukla S(2018)Asynchronous hardware implementations for crypto primitivesMicroprocessors and Microsystems10.1016/j.micpro.2018.11.002Online publication date: Nov-2018
https://doi.org/10.1016/j.micpro.2018.11.002
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