Article

Exact minimum-width transistor placement without dual constraint for CMOS cells

Authors:

Tetsuya Iizuka,

Makoto Ikeda,

Kunihiro AsadaAuthors Info & Claims

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

Pages 74 - 77

https://doi.org/10.1145/1057661.1057681

Published: 17 April 2005 Publication History

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Abstract

This paper proposes flat and hierarchical approaches for generating a minimum-width transistor placement of CMOS cells in presence of non-dual P and N type transistors. Our approaches are the first exact method which can be applied to CMOS cells with any types of structure. We formulate the transistor placement problem into Boolean Satisfiability (SAT) problem considering the P and N type transistors individually. The experimental results show that our flat approach generates smaller width placement for 29 out of 103 dual cells than that of the conventional method, and the width of only 3 out of 147 cells solved by our hierarchical approach are larger than that of the flat approach. Using the hierarchical approach, 81% of 340 cells in an industrial standard-cell library of 90 nm technology are solved within one hour for each cell, whereas 32% using the conventional exact method.

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Cited By

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Cardoso MSmaniotto GBubolz Ada Rosa Junior Lde Marques F(2018)Area-Aware Design of Static CMOS Complex Gates2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)10.1109/NEWCAS.2018.8585570(282-286)Online publication date: Jun-2018
https://doi.org/10.1109/NEWCAS.2018.8585570
Cardoso MSmaniotto GMachado JMoreira Mda Rosa LMarques F(2017)Transistor placement strategies for non-series-parallel cells2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2017.8052975(523-526)Online publication date: Aug-2017
https://doi.org/10.1109/MWSCAS.2017.8052975
Lu ALu HJang ELin YHung CChuang CLin RNebel WAtienza D(2015)Simultaneous transistor pairing and placement for CMOS standard cellsProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757194(1647-1652)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2757194
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Index Terms

Exact minimum-width transistor placement without dual constraint for CMOS cells
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Partitioning and floorplanning

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Published In

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

April 2005

518 pages

ISBN:1595930574

DOI:10.1145/1057661

General Chair:
John Lach
University of Virginia
,
Program Chairs:
Gang Qu
University of Maryland, College Park
,
Yehea Ismail
Northwestern University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 17 April 2005

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April 17 - 19, 2005

Illinois, Chicago, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cardoso MSmaniotto GBubolz Ada Rosa Junior Lde Marques F(2018)Area-Aware Design of Static CMOS Complex Gates2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)10.1109/NEWCAS.2018.8585570(282-286)Online publication date: Jun-2018
https://doi.org/10.1109/NEWCAS.2018.8585570
Cardoso MSmaniotto GMachado JMoreira Mda Rosa LMarques F(2017)Transistor placement strategies for non-series-parallel cells2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2017.8052975(523-526)Online publication date: Aug-2017
https://doi.org/10.1109/MWSCAS.2017.8052975
Lu ALu HJang ELin YHung CChuang CLin RNebel WAtienza D(2015)Simultaneous transistor pairing and placement for CMOS standard cellsProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757194(1647-1652)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2757194
Cardoso Mda Rosa Lde Souza Marques Fde Lima RCunha APlett Cde Oliveira W(2015)Evaluating Geometric Aspects of Non-Series-Parallel CellsProceedings of the 28th Symposium on Integrated Circuits and Systems Design10.1145/2800986.2801008(1-6)Online publication date: 31-Aug-2015
https://dl.acm.org/doi/10.1145/2800986.2801008
Posser GZiesemer AGuimares DWilke GReis R(2010)A study on layout quality of automatic generated cells2010 17th IEEE International Conference on Electronics, Circuits and Systems10.1109/ICECS.2010.5724596(651-654)Online publication date: Dec-2010
https://doi.org/10.1109/ICECS.2010.5724596
Iizuka TIkeda MAsada K(2006)Exact minimum-width multi-row transistor placement for dual and non-dual CMOS cells2006 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2006.1693862(4)Online publication date: 2006
https://doi.org/10.1109/ISCAS.2006.1693862

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SAT-Based Placement Adjustment of FinFETs inside Unroutable Standard Cells Targeting Feasible DRC-Clean Routing

Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells

Simultaneous transistor pairing and placement for CMOS standard cells

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