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High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping

Published: 17 April 2005 Publication History

Abstract

We develop a novel on-line built-in self-test (BIST) technique for testing FPGAs that has a very high diagnosability, even in presence of clustered faults, a fault pattern for which previous BIST methods proved ineffective. Unlike previous BIST methods which unrealistically assume that the test circuitry used for testing PLBs is fault-free, our method, via an iterative bootstrapping process, first finds this fault-free test circuitry and then starts testing the PLBs. Also, unlike previous methods, our fault detection process does not require any unrealistic assumptions of fault-free status of some components or the existence of only some fault patterns (and the exclusion of others) in the FPGA. Our adaptive fault diagnosis process is more time efficient than its previous counterparts as it does not require testing of all the PLBs of a faulty BIST area, and its design is simpler in the sense that it does not require multiple modifications of the testing area for its implementation. We also analyze the probability of correct diagnosis in the presence of multiple faults. Our BIST technique gives excellent fault coverage and fault latency results, and supports the theoretical analysis.

References

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V. Verma, S. Dutt and V. Suthar, "Efficient On-line Testing of FPGAs with Provable Diagnosabilities," Proc. DAC, 2004 pp 498--503.
[2]
M. Abramovici, C. Stroud, B. Skaggs and J. Emmert, "Improving online BIST-based diagnosis for roving STARs", Proc. 6th IEEE Intl Online Testing Workshop, 2000, pp 31--39.
[3]
N. R. Shnidman, W. H. Mangione-Smith, and M. Potkonjak, "On-line Fault Detection for Bus-Based Field Programmable Gate Arrays," IEEE Trans. on VLSI systems, Vol. 6, No. 4, pp 656--666, Dec 1998.
[4]
W. K. Huang, F. J. Meyer, X. Chen and F. Lombardi, "Testing configurable LUT-Based FPGAs", IEEE Trans. VLSI, Vol. 6, pp 276--283.
[5]
S. J. Wang and T. M. Tai, "Test and Diagnosis of Faulty Logic Blocks in FPGAs", Proc. ICCAD, 1987.
[6]
W. K. Huang and F.Lombardi, "An approach to testing of Programmable/Configurable FPGAs," Proc. VTS, pp. 450--455, 1996.
[7]
A. Steininger and C. Scherrer, "On the Necessity of On-Line BIST in Safety-Critical Applications," Proc. 29th FTCS., pp. 208--215, 1999.
[8]
A. Burress and P. Lala, "On-Line Testable Logic Design for FPGA Implementation.," Proc. Intn'l Test Conf., pp. 471--478, 1997.

Cited By

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  • (2006)Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faultsProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131803(1165-1170)Online publication date: 6-Mar-2006
  • (2006)Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free AssumptionsProceedings of the 24th IEEE VLSI Test Symposium10.1109/VTS.2006.47(36-43)Online publication date: 30-Apr-2006
  • (2006)Efficient On-line Interconnect Testing in FPGAs with Provable Detectability for Multiple FaultsProceedings of the Design Automation & Test in Europe Conference10.1109/DATE.2006.244017(1-6)Online publication date: 2006

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  1. High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping

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        cover image ACM Conferences
        GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI
        April 2005
        518 pages
        ISBN:1595930574
        DOI:10.1145/1057661
        • General Chair:
        • John Lach,
        • Program Chairs:
        • Gang Qu,
        • Yehea Ismail
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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        Published: 17 April 2005

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        Author Tags

        1. FPGAs
        2. built-in self-tester (BISTer)
        3. diagnosability
        4. functional testing
        5. on-line testing
        6. roving tester (ROTE)

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        GLSVLSI05: Great Lakes Symposium on VLSI 2005
        April 17 - 19, 2005
        Illinois, Chicago, USA

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        Overall Acceptance Rate 312 of 1,156 submissions, 27%

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        View all
        • (2006)Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faultsProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131803(1165-1170)Online publication date: 6-Mar-2006
        • (2006)Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free AssumptionsProceedings of the 24th IEEE VLSI Test Symposium10.1109/VTS.2006.47(36-43)Online publication date: 30-Apr-2006
        • (2006)Efficient On-line Interconnect Testing in FPGAs with Provable Detectability for Multiple FaultsProceedings of the Design Automation & Test in Europe Conference10.1109/DATE.2006.244017(1-6)Online publication date: 2006

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