Article

An FPGA design of AES encryption circuit with 128-bit keys

Authors:

Hui Qin,

Tsutomu Sasao,

Yukihiro IguchiAuthors Info & Claims

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

Pages 147 - 151

https://doi.org/10.1145/1057661.1057697

Published: 17 April 2005 Publication History

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Abstract

This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. Using the proposed architecture on the Altera Stratix EP1S20F780C5 FPGA, the AES-4SM achieves a throughput of 5.61 Gbps by using 20 M4Ks, and the AES-8SM achieves a throughput of 10.49 Gbps by using 40 M4Ks. Compared with the unrolling implementation that achieves a throughput of 20.48 Gbps by using 80 M4Ks on the same FPGA, implementations with the PPR architecture reduce the amount of memory up to 75% while increasing the memory efficiency (i.e., throughput divided by the size of memory for core) up to 9.6%.The PPR architecture.lls the gap between unrolling and rolling architectures,and.ts on less expensive FPGAs.

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Cited By

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Qin JWang YLi LYang SZhang X(2024)P-AES: Advanced Encryption Standard Parallel Optimization on MGPUSim2024 IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA)10.1109/ISPA63168.2024.00271(1988-1993)Online publication date: 30-Oct-2024
https://doi.org/10.1109/ISPA63168.2024.00271
Priya.N HS M AS SRathika P(2021)Improving Security with Federated Learning2021 International Conference on Computational Performance Evaluation (ComPE)10.1109/ComPE53109.2021.9752023(234-239)Online publication date: 1-Dec-2021
https://doi.org/10.1109/ComPE53109.2021.9752023
Youness H(2019)Speedup for Cryptography on CUDA Heterogeneous Architecture2019 International Conference on Innovative Trends in Computer Engineering (ITCE)10.1109/ITCE.2019.8646497(92-97)Online publication date: Feb-2019
https://doi.org/10.1109/ITCE.2019.8646497
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Index Terms

An FPGA design of AES encryption circuit with 128-bit keys
1. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific processors

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Published In

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

April 2005

518 pages

ISBN:1595930574

DOI:10.1145/1057661

General Chair:
John Lach
University of Virginia
,
Program Chairs:
Gang Qu
University of Maryland, College Park
,
Yehea Ismail
Northwestern University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 17 April 2005

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GLSVLSI05: Great Lakes Symposium on VLSI 2005

April 17 - 19, 2005

Illinois, Chicago, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Qin JWang YLi LYang SZhang X(2024)P-AES: Advanced Encryption Standard Parallel Optimization on MGPUSim2024 IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA)10.1109/ISPA63168.2024.00271(1988-1993)Online publication date: 30-Oct-2024
https://doi.org/10.1109/ISPA63168.2024.00271
Priya.N HS M AS SRathika P(2021)Improving Security with Federated Learning2021 International Conference on Computational Performance Evaluation (ComPE)10.1109/ComPE53109.2021.9752023(234-239)Online publication date: 1-Dec-2021
https://doi.org/10.1109/ComPE53109.2021.9752023
Youness H(2019)Speedup for Cryptography on CUDA Heterogeneous Architecture2019 International Conference on Innovative Trends in Computer Engineering (ITCE)10.1109/ITCE.2019.8646497(92-97)Online publication date: Feb-2019
https://doi.org/10.1109/ITCE.2019.8646497
Karthigaikumar PAnitha Christy NSiva Mangai N(2015)PSP CO2Wireless Personal Communications: An International Journal10.1007/s11277-015-2739-x85:1(305-323)Online publication date: 1-Nov-2015
https://dl.acm.org/doi/10.1007/s11277-015-2739-x
Rahimunnisa KKarthigaikumar PChristy NKumar SJayakumar J(2013)PSP: Parallel sub-pipelined architecture for high throughput AES on FPGA and ASICOpen Computer Science10.2478/s13537-013-0112-23:4Online publication date: 1-Jan-2013
https://doi.org/10.2478/s13537-013-0112-2
Li QZhong CZhao KMei XChu X(2012)Implementation and Analysis of AES Encryption on GPUProceedings of the 2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems10.1109/HPCC.2012.119(843-848)Online publication date: 25-Jun-2012
https://dl.acm.org/doi/10.1109/HPCC.2012.119
Gupta AAhmad ASharif MAmira A(2011)Rapid prototyping of AES encryption for wireless communication system on FPGA2011 IEEE 15th International Symposium on Consumer Electronics (ISCE)10.1109/ISCE.2011.5973895(571-575)Online publication date: Jun-2011
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Nishikawa NIwai KKurokawa T(2011)High-Performance Symmetric Block Ciphers on CUDAProceedings of the 2011 Second International Conference on Networking and Computing10.1109/ICNC.2011.40(221-227)Online publication date: 30-Nov-2011
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Soliman MAbozaid G(2011)FPGA implementation and performance evaluation of a high throughput crypto coprocessorJournal of Parallel and Distributed Computing10.1016/j.jpdc.2011.04.00671:8(1075-1084)Online publication date: 1-Aug-2011
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Tana HSazish AAhmad ASharif MAmira A(2010)Efficient FPGA implementation of a wireless communication system using Bluetooth connectivityProceedings of 2010 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2010.5537610(1767-1770)Online publication date: May-2010
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Recommendations

A fully pipelined memoryless 17.8 Gbps AES-128 encryptor

A Design of AES Encryption Circuit with 128-bit Keys Using Look-Up Table Ring on FPGA

An FPGA implementation for neural networks with the FDFM processor core approach

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