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Interconnect capacitance extraction for system LCD circuits

Published: 17 April 2005 Publication History

Abstract

This paper discusses interconnect capacitance extraction for system LCD circuits, where coupling capacitance is much significant since a ground plane locates far away unlike LSI interconnects. We focus on a pattern matching method with interpolation to implement an accurate and efficient capacitance extraction system, and present good implementations that are suitable for system LCD circuits. To reduce computational cost, interconnect structures are spatially divided into several sub-regions considering capacitance coupling range, and analyzed in each sub-region using a capacitance database pre-characterized by a 3-D field solver. This paper evaluates tradeoff curves between characterization cost and extraction accuracy for four division methods in lattice structures that are basic and common structures in LCD driver circuits. Experimental results reveal efficient division methods for accurate capacitance extraction.

References

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Cited By

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  • (2022)A Secant Method Based Fixed-Resistance Routing Approach for the Design of Flat Panel DisplayJournal of Computer-Aided Design & Computer Graphics10.3724/SP.J.1089.2022.1889934:03(325-331)Online publication date: 2-Dec-2022
  • (2017)Efficient algorithms for resistance and capacitance calculation problems in the design of flat panel display: [Invited paper]2017 IEEE 12th International Conference on ASIC (ASICON)10.1109/ASICON.2017.8252640(973-976)Online publication date: Oct-2017
  • (2016)A Parallel Random Walk Solver for the Capacitance Calculation Problem in Touchscreen DesignProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2903011(99-104)Online publication date: 18-May-2016
  • Show More Cited By

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  1. Interconnect capacitance extraction for system LCD circuits

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    cover image ACM Conferences
    GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI
    April 2005
    518 pages
    ISBN:1595930574
    DOI:10.1145/1057661
    • General Chair:
    • John Lach,
    • Program Chairs:
    • Gang Qu,
    • Yehea Ismail
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 17 April 2005

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    Author Tags

    1. capacitance extraction
    2. interconnect capacitance
    3. system LCD

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    GLSVLSI05: Great Lakes Symposium on VLSI 2005
    April 17 - 19, 2005
    Illinois, Chicago, USA

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    Overall Acceptance Rate 312 of 1,156 submissions, 27%

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    View all
    • (2022)A Secant Method Based Fixed-Resistance Routing Approach for the Design of Flat Panel DisplayJournal of Computer-Aided Design & Computer Graphics10.3724/SP.J.1089.2022.1889934:03(325-331)Online publication date: 2-Dec-2022
    • (2017)Efficient algorithms for resistance and capacitance calculation problems in the design of flat panel display: [Invited paper]2017 IEEE 12th International Conference on ASIC (ASICON)10.1109/ASICON.2017.8252640(973-976)Online publication date: Oct-2017
    • (2016)A Parallel Random Walk Solver for the Capacitance Calculation Problem in Touchscreen DesignProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2903011(99-104)Online publication date: 18-May-2016
    • (2016)The application of boundary element method to the resistance calculation problem in designing flat panel displaysJournal of the Society for Information Display10.1002/jsid.42924:3(177-186)Online publication date: 22-Apr-2016

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