Article

Two-prime RSA immune cryptosystem and its FPGA implementation

Authors:

Y. Yang,

Z. Abid,

W. WangAuthors Info & Claims

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

Pages 164 - 167

https://doi.org/10.1145/1057661.1057701

Published: 17 April 2005 Publication History

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Abstract

In this paper, an efficient immunity method is proposed for two-prime RSA cryptosystem against hardware fault attack. The proposed system has more immunity than the previous system and is targeted for FPGA implementation. For the 32-bit signing case, the proposed method is 15% faster than the previous design while requiring only 70% of the hardware resource.

References

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J. Grossschadl, "The Chinese Remainder Theorem and its application in a high-speed RSA crypto chip," Computer Security Applications, 16th Annual Conference, New Orleans, USA, Dec. 2000, pp. 384--393.

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RSA Laboratories, "PKCS #1 v2.0 Amendment 1: Multi-Prime RSA," July 2000. Available: ftp://ftp.rsasecurity.com/pub/pkcs/pkcs-1/pkcs-1v2-0a1.pdf

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Krishnamurthy, Y. Tang, C. Xu and Y. Wang, "An Efficient Implementation of Multi-Prime RSA on Dsp Processor," IEEE Int. Con. on Acoustics, Speech, & Signal Processing, vol. 2, pp 413--416, April 2003.

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C.-H. Wu, J.-H. Hong and C. W. Wu, "RSA cryptosystem design based on the Chinese Remainder Theorem," Proceedings of the ASP-DAC 2001, Las Vegas, USA, Jan-Feb. 2001, pp. 391--395.

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A. Shamir, "How to Check Modular Exponentiation," EUROCRYPT '97, May 1997.

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S. Yen, S. Kim, S. Lim and S. Moon, "RSA Speedup with Chinese Remainder Theorem Immune against Hardware Fault Cryptanalysis," IEEE Transactions on computers, vol. 52, pp 461--472, April 2003.

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Index Terms

Two-prime RSA immune cryptosystem and its FPGA implementation
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

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Published In

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

April 2005

518 pages

ISBN:1595930574

DOI:10.1145/1057661

General Chair:
John Lach
University of Virginia
,
Program Chairs:
Gang Qu
University of Maryland, College Park
,
Yehea Ismail
Northwestern University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 April 2005

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GLSVLSI05: Great Lakes Symposium on VLSI 2005

April 17 - 19, 2005

Illinois, Chicago, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Abstract

References

Index Terms

Recommendations

Efficient hardware implementation of RSA cryptography

Revisiting Prime Power RSA

Efficient key management FPGA-based cryptosystem using the RNS and iterative coding

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