skip to main content
10.1145/1057661.1057703acmconferencesArticle/Chapter ViewAbstractPublication PagesglsvlsiConference Proceedingsconference-collections
Article

Digital cell macro-model with regular substrate template and EKV based MOSFET model

Published: 17 April 2005 Publication History

Abstract

This paper presents substrate noise macro-models for standard digital cells, like INV, NAND and BUFFER. The macro-models are based on a scalable substrate network template and a compact MOSFET model equivalent to EKV model. Our models and simulator predicted the substrate voltage, injection currents, and output voltage of each primary digital cell. Proposed models are close to device physics and valid for different processing technology and input transition. They are more accurate as compared to macro-models generated from curve fitting. Our macro-model accuracy is within 5-10% from SPICE simulation with MOSFET level49 models, and at least 4 times faster. This model can be used to predict spatially and temporally the occurrence of substrate noise peaks in a digital design.

References

[1]
X. Aragones et al, Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs, Kluwer, 1999.
[2]
A. Samavedam et al, "A Scalabel Substrate Noise Coupling Model for Design of Mixed-Signal IC's", JSSC, Vol.35, No. 6, June 2000.
[3]
R. Gharpurey et al, "Modeling and Analysis of Substrate coupling in integrated circuits", Journal of Solid-state Circuits, Vol. 31, No.3, March 1996.
[4]
M. Badaroglu et. al., "High-Level Simulation of Substrate Noise Generation from Large Digital Circuits with multiple Supplies", Proc. DATE, 2001, pp. 326--330.
[5]
A. Koyama et al, "Switching Well Noise Modeling and Minimization Strategy for Digital Circuits with a Controllable Threshold Voltage Scheme", IEEE Trans. CAD, Vol.19, No.6,June 2000, pp. 654--670.
[6]
C. Enz et al, "An analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low-Voltage and Low-Current Applications", Analog Integrated Circuits and Signal Processing", Kluwer, 1995.
[7]
Tanner Consulting and Engineering Services, Digital Low Power Standard Cell Library.
[8]
N.P. van der Meijs et al, SPACE USER's Manual, May 2003. D. Foty, MOSFET modeling with Spice, Prentence Hall, 1997.
[9]
Yulei, Alex Doboli, "Regularity Based Extraction of Substrate Noise Coupling and Symbolic Digital Noise Simulation with EK Transistor Model", Technical report (submitted to DAC05).
[10]
Steven C. Chapra, Raymond Canale, Numerical Methods for Engineers.
  1. Digital cell macro-model with regular substrate template and EKV based MOSFET model

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI
    April 2005
    518 pages
    ISBN:1595930574
    DOI:10.1145/1057661
    • General Chair:
    • John Lach,
    • Program Chairs:
    • Gang Qu,
    • Yehea Ismail
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 17 April 2005

    Permissions

    Request permissions for this article.

    Check for updates

    Qualifiers

    • Article

    Conference

    GLSVLSI05
    Sponsor:
    GLSVLSI05: Great Lakes Symposium on VLSI 2005
    April 17 - 19, 2005
    Illinois, Chicago, USA

    Acceptance Rates

    Overall Acceptance Rate 312 of 1,156 submissions, 27%

    Upcoming Conference

    GLSVLSI '25
    Great Lakes Symposium on VLSI 2025
    June 30 - July 2, 2025
    New Orleans , LA , USA

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • 0
      Total Citations
    • 153
      Total Downloads
    • Downloads (Last 12 months)0
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 07 Mar 2025

    Other Metrics

    Citations

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Figures

    Tables

    Media

    Share

    Share

    Share this Publication link

    Share on social media