skip to main content
10.1145/1057661.1057707acmconferencesArticle/Chapter ViewAbstractPublication PagesglsvlsiConference Proceedingsconference-collections
Article

Two dimensional reordering of functional test data for compression by ATE

Published: 17 April 2005 Publication History

Abstract

This paper presents a novel approach for compressing functional test data in Automatic Test Equipment (ATE). A practical technique is presented for 2 Dimensional (2D) reordering of test data in which additionally to test vector reordering, column reordering is also applied. An ATE based approach to extract the original test vectors from the 2D ordered data is presented. The advantage of the approach is substantiated using the figure of merit of entropy for the 2D ordered test data of ISCAS benchmark circuits.

References

[1]
Y. Zorian, "Test Requirements for Embedded Core-Based Systems and IEEE P1500," Proc. Intl. Test Conf., pp. 191--199, 1997.
[2]
I. Pomeranz, L. Reddy and S. M. Reddy, "Compactest: A Method to Generate Compact Test Sets for Combinational Circuits," Proc. of Intl. Test Conf., pp. 194--203, 1991.
[3]
J.-S. Chang and C.-S. Lin, "Test Set Compaction for Combinational Circuits," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, pp. 1370--1378, Nov. 1995.
[4]
I. Hamzaoglu and J. H. Patel, "Test Set Compaction Algorithms for Combinational Circuits," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No. 8, pp. 957--963, Aug. 2000.
[5]
A. El-Maleh, S. Al-Zahir and E. Kahn, "A Geometric Primitive Based Compression Scheme for Testing System-on-a-Chip," Proc. IEEE VLSI Test Symp., pp. 54--59, 2001.
[6]
T. Yamaguchi, M. Ishida and D. S. Ha, "An Efficient Method for Compressing Test Data," Proc. IEEE Intl. Test Conf., pp. 79--88, 1997.
[7]
A. Jas and N. A. Touba, "Test Vector Decompression via Cyclical Scan Chains and Its Application to Testing Core-Based Designs," Proc. IEEE Intl. Test Conf., pp. 458--464, 1998.
[8]
A. Chandra and K. Chakrabarty, "System-on-a-chip test-data compression and decompression architectures based on Golomb codes," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 3, pp. 355--368, March 2001.
[9]
P. T. Gonciari, B. M. Al-Hashimi and N. Nicolici "Variable-Length Input Huffman Coding for System-on-a-Chip Test," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 6, pp. 783--796, June 2003.
[10]
A. Jas, J. G. Dastidar, N. M. Eng and N. A. Touba, "An efficient test vector compression scheme using selective Huffman coding," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 6, pp. 797--806, June 2003.
[11]
F. Karimi, Z. Navabi, W. M. Meleis and F. Lombardi, "Using Data Compression in Automatic Test Equipment for System-on-Chip Testing," IEEE Trans. on Instrumentation and Measurement, Vol. 53, No. 2, pp. 308--317, April 2004.
[12]
H. Hashempour and F. Lombardi, "ATE-Amenable Test Data Compression With no Cyclic Scan Registers," Proc. IEEE Intl. Conf. On Defect and Fault Tolerance in VLSI Systems, pp. 151--158, 2003.
[13]
T. Alton, "TGEN: Flexible Timing Generator Architecture," Proc. IEEE Intl. Test Conf., pp. 439--443, 1992.
[14]
M. L. Bushnell and V. D. Agrawal, "Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits," Kluwer Academic Pub., 2000.
[15]
K. Helsgaun, "An Effective Implementation of the Lin-Kernighan Traveling Salesman Heuristic," European Journal of Operational Research 126 (1), 106--130 (2000).

Cited By

View all
  • (2010)Hamming Distance Based 2-D Reordering with Power Efficient Don't Care Bit Filling: Optimizing the test data compression method2010 International Symposium on System on Chip10.1109/ISSOC.2010.5625560(1-7)Online publication date: Sep-2010

Index Terms

  1. Two dimensional reordering of functional test data for compression by ATE

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI
    April 2005
    518 pages
    ISBN:1595930574
    DOI:10.1145/1057661
    • General Chair:
    • John Lach,
    • Program Chairs:
    • Gang Qu,
    • Yehea Ismail
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 17 April 2005

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. 2D reordering
    2. ATE
    3. column reordering
    4. functional test data
    5. scan test data
    6. test data compression

    Qualifiers

    • Article

    Conference

    GLSVLSI05
    Sponsor:
    GLSVLSI05: Great Lakes Symposium on VLSI 2005
    April 17 - 19, 2005
    Illinois, Chicago, USA

    Acceptance Rates

    Overall Acceptance Rate 312 of 1,156 submissions, 27%

    Upcoming Conference

    GLSVLSI '25
    Great Lakes Symposium on VLSI 2025
    June 30 - July 2, 2025
    New Orleans , LA , USA

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)4
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 01 Mar 2025

    Other Metrics

    Citations

    Cited By

    View all
    • (2010)Hamming Distance Based 2-D Reordering with Power Efficient Don't Care Bit Filling: Optimizing the test data compression method2010 International Symposium on System on Chip10.1109/ISSOC.2010.5625560(1-7)Online publication date: Sep-2010

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Figures

    Tables

    Media

    Share

    Share

    Share this Publication link

    Share on social media