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Fine-grain leakage optimization in SRAM based FPGAs

Published: 17 April 2005 Publication History

Abstract

FPGAs are evolving at a rapid pace with improved performance and logic density. At the same time, trends in technology scaling makes leakage power a serious concern for designers. In this paper, we propose a hierarchical look-up table (LUT) structure for FPGAs to improve leakage power consumption. We present a detailed analysis on the number of inputs actually used by LUTs, and we observe that on an average 47% LUTs do not use one or more inputs. In the proposed hierarchical LUT structure depending on the number of inputs used by the LUTs we shut off certain SRAM cells and transistors associated with the unused LUT inputs. Based on this technique, for 180nm technology, we report an average savings of 22.94% (as high as 64.22%) in leakage power per LUT. The savings will be even greater for technologies as low as 90nm currently in use for FPGA production as well as for future technologies.

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  • (2014)Adaptive Energy Management for Dynamically Reconfigurable ProcessorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.228226533:1(50-63)Online publication date: 1-Jan-2014
  • (2013)A novel productivity-driven logic element for field-programmable devicesInternational Journal of Electronics10.1080/00207217.2013.794489101:6(731-762)Online publication date: 9-Jul-2013
  • (2012)Adaptive power management of on-chip video memory for multiview video codingProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228516(866-875)Online publication date: 3-Jun-2012
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      cover image ACM Conferences
      GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI
      April 2005
      518 pages
      ISBN:1595930574
      DOI:10.1145/1057661
      • General Chair:
      • John Lach,
      • Program Chairs:
      • Gang Qu,
      • Yehea Ismail
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 17 April 2005

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      Author Tags

      1. FPGA
      2. hierarchical LUT
      3. leakage power
      4. low power

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      GLSVLSI05: Great Lakes Symposium on VLSI 2005
      April 17 - 19, 2005
      Illinois, Chicago, USA

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      Overall Acceptance Rate 312 of 1,156 submissions, 27%

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      Cited By

      View all
      • (2014)Adaptive Energy Management for Dynamically Reconfigurable ProcessorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.228226533:1(50-63)Online publication date: 1-Jan-2014
      • (2013)A novel productivity-driven logic element for field-programmable devicesInternational Journal of Electronics10.1080/00207217.2013.794489101:6(731-762)Online publication date: 9-Jul-2013
      • (2012)Adaptive power management of on-chip video memory for multiview video codingProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228516(866-875)Online publication date: 3-Jun-2012
      • (2011)A low-power memory architecture with application-aware power management for motion & disparity estimation in multiview video codingProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132335(40-47)Online publication date: 7-Nov-2011
      • (2011)A low-power memory architecture with application-aware power management for motion & disparity estimation in Multiview Video CodingProceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design10.1109/ICCAD.2011.6105303(40-47)Online publication date: 7-Nov-2011
      • (2010)Selective instruction set muting for energy-aware adaptive processorsProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133505(353-360)Online publication date: 7-Nov-2010
      • (2010)Selective instruction set muting for energy-aware adaptive processors2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2010.5653636(353-360)Online publication date: Nov-2010
      • (2010)A novel HDL coding style to reduce power consumption for reconfigurable devices2010 International Conference on Field-Programmable Technology10.1109/FPT.2010.5681480(295-299)Online publication date: Dec-2010
      • (2006)Power Optimization Techniques for SRAM-Based FPGAs2006 International Conference on Field Programmable Logic and Applications10.1109/FPL.2006.311362(1-2)Online publication date: Aug-2006

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