Energy management in software-controlled multi-level memory hierarchies
Authors: 
O. Ozturk, M. KandemirAuthors Info & Claims
O. Ozturk, M. KandemirAuthors Info & ClaimsPages 270 - 275
Abstract
Performance and energy consumption behavior of embedded applications are increasingly being dependent on their memory usage/access patterns. Focusing on a software-managed, application-specific multi-level memory hierarchy, this paper studies three different memory hierarchy management schemes from both energy and performance angles. The first scheme is pure performance-oriented and tuned for extracting the maximum performance possible from the software-managed multi-level memory hierarchy. The second scheme is built upon the first one but it also reduces leakage by turning-on and off memory modules (i.e., different memory levels) at appropriate program points during execution based on the data access pattern information extracted by the compiler. The last scheme evaluated is oriented towards further reducing leakage energy, as well as dynamic energy, by modifying the data transfer policy (data access pattern) of the performance-oriented scheme. Our empirical analysis indicates that it is possible to reduce leakage consumption of the application-specific multi-level memory hierarchy without seriously impacting its performance, and that one can achieve further savings by modifying data transfer pattern across the different levels of the memory hierarchy.
References
[1]
The CACTI tool-set. http://research.compaq.com/wrl/people/jouppi/CACTI.html
[2]
F. Catthoor, F. Franssen, S. Wuytack, L. Nachtergaele, and H. De Man. Global communication and memory optimizing transformations for low power signal processing systems. In Proc. IEEE Workshop on VLSI Signal Processing, pages 178--187, 1994.
[3]
F. Catthoor, S. Wuytack, E. D. Greef, F. Balasa, L. Nachtergaele, and A. Vandecappelle. Custom memory management methodology - exploration of memory organization for embedded multimedia system design. Kluwer Academic Publishers, June, 1998.
[4]
A. Chandrakasan, W. J. Bowhill, and F. Fox. Design of High-Performance Microprocessor Circuits. IEEE Press, 2001.
[5]
M. Cierniak and W. Li. Inter-procedural array re-mapping. In Proc. the International Conference on Parallel Architectures and Compilation Techniques, November 1997.
[6]
K. Flautner, N. Kim, S. Martin, D. Blaauw, T. Mudge. Drowsy Caches: Simple techniques for reducing leakage power. In Proc. the 29th International Symposium on Computer Architecture, Anchorage, AK, May 2002.
[7]
F. Gharsalli, S. Meftali, F. Rousseau, and A. A. Jerraya. Automatic generation of embedded memory wrapper for multiprocessor SoC. In Proc. the 39th Design Automation Conference, New Orleans, Louisiana, 1999.
[8]
S. Ghosh, M. Martonosi, and S. Malik. Precise miss analysis for program transformations with caches of arbitrary associativity. In Proc. 8th International Symposium on Architectural Support for Programming Languages and Operating Systems, October, 1998.
[9]
M. W. Hall, J. M. Anderson, S. P. Amarasinghe, B. R. Murphy, S.-W. Liao, E. Bugnion, and M. S. Lam. Maximizing multiprocessor performance with the SUIF compiler. IEEE Computer, December 1996.
[10]
H. Hanson, M. S. Hrishikesh, V. Agarwal, S. W. Keckler, and D. Burger. Static energy reduction techniques for microprocessor caches. In Proc. the 2001 International Conference on Computer Design, 2001.
[11]
S. Heo, K. Barr, M. Hampton, and K. Asanovic. Dynamic Fine-Grain Leakage Reduction using Leakage-Biased Bitlines. In Proc. the 29th International Symposium on Computer Architecture, Anchorage, AK, May 2002.
[12]
M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and W. Ye. Influence of compiler optimizations on system power. In Proc. the 37th Design Automation Conference (DAC'00), Los Angeles, CA, June 5-9, 2000.
[13]
S. Kaxiras, Z. Hu, M. Martonosi. Cache decay: exploiting generational behavior to reduce cache leakage power. In Proc. the 28th International Symposium on Computer Architecture, Sweden, June 2001.
[14]
N. S. Kim, K. Flautner, D. Blaauw, and T. Mudge. Drowsy instruction caches. Proceedings of the 35th International Symposium on Microachitecture, 2002.
[15]
L. Li, I. Kadayif, Y-F. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, and A. Sivasubramaniam. Leakage energy management in cache hierarchies. In Proc. the Eleventh International Conference on Parallel Architectures and Compilation Techniques, Charlottesville, Virginia, September, 2002.
[16]
K. McKinley, S. Carr, and C.W. Tseng. Improving data locality with loop transformations. ACM Trans. on Programming Languages and Systems, 1996.
[17]
S. Meftali, F. Gharsalli, F. Rousseau, and A. A. Jerraya. An optimal memory allocation for application-specific multiprocessor system-on-chip. In Proc. the International Symposium on Systems Synthesis, Montreal, Canada, 2001.
[18]
M. D. Powell, S. Yang, B. Falsafi, K. Roy, and T. N. Vijaykumar. Reducing Leakage in a High-Performance Deep-Submicron Instruction Cache. IEEE Transactions on VLSI, Vol. 9, No. 1, February 2001.
[19]
The SimpleScalar tool-set. http://www.simplescalar.com/
[20]
W. Zhang, J. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. Compiler-directed instruction cache leakage optimization. In Proc. the 35th Annual International Symposium on Microarchitecture, November 2002.
[21]
W. Zhang, M. Karakoy, M. Kandemir, and G. Chen. A compiler approach for reducing data cache enrgy. In Proc. the 17th International Conference on Supercomputing, San FRancisco, CA, June 2003.
[22]
H. Zhou, M. C. Toburen, E. Rotenberg, and T. M. Conte. Adaptive mode control: a static power-efficient cache design. In Proc. the International Conference on Parallel Architectures and Compilation Techniques, 2001.
Index Terms
- Energy management in software-controlled multi-level memory hierarchies
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Published: 17 April 2005
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