Article

An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs

Authors:

Chin-Cheng Kuo,

Yu-Chien Wang,

Chien-Nan Jimmy LiuAuthors Info & Claims

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

Pages 286 - 290

https://doi.org/10.1145/1057661.1057730

Published: 17 April 2005 Publication History

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Abstract

In this paper, an efficient bottom-up extraction approach is presented to generate accurate behavioral models of PLL circuits more quickly by using Verilog-AMS language. Not only top-down applications but also bottom-up applications can be supported by using our PLL models. The main idea is to use a special "characterization mode" to get critical circuit parameters. In the characterization mode, only two input patterns are enough to get circuit properties with parasitic effects. In the experimental results, we will build an accurate PLL behavioral models for demonstration compared to the HSPICE results and typical behavioral models.

References

[1]

Open Verilog International, "Verilog-AMS Language Reference Manual 2.1", January 2003.

Google Scholar

[2]

IEEE Standard VHDL Analog and Mixed-Signal Extensions (IEEE Standard 1076.1--1999), December, 1999.

Google Scholar

[3]

Manganaro, G.; Sung Ung Kwak; SeongHwan Cho; Pulincherry, A.; "A behavioral modeling approach to the design of a low jitter clock source", Circuits and Systems II: Analog and Digital Signal Processing, Nov. 2003.

Crossref

Google Scholar

[4]

Hinz, M.; Konenkamp, I.; Horneber, E.-H.; "Behavioral modeling and simulation of phase-locked loops for RF front ends", Circuits and Systems, Aug. 2000.

Crossref

Google Scholar

[5]

Karray, M.; Seon, J.K.; Charlot, J.-J.; Nasmoudi, N.; "VHDL-AMS modeling of a new PLL with an inverse sine phase detector", BMAS, Oct. 2002.

Google Scholar

[6]

A. Mounir; A. Mostafa; M. Fikry; "Automatic Behavioural Model Calibration for Efficient PLL System Verification", DATE, 2003.

Digital Library

Google Scholar

[7]

B. A. A. Antao; F. M. El-Turky; R. H. Leonowich; "Behavioral modeling phase-locked loops for mixed-mode simulation", Analog Integrated Circuits and Signal Processing, 1996.

Digital Library

Google Scholar

[8]

Crippa, P.; Turchetti, C.; Conti, M.; "A statistical methodology for the design of high-performance CMOS current-steering digital-to-analog converters", Computer-Aided Design of Integrated Circuits and Systems, April 2002.

Digital Library

Google Scholar

[9]

Felt, E.; Zanella, S.; Guardiani, C.; Sangiovanni-Vincentelli, A.; "Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling", ICCAD, Nov. 1996.

Digital Library

Google Scholar

Cited By

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Song LLou YLin CLiu CHuang JJou JLee MLo Y(2021)Efficient Circuit Structure Analysis for Automatic Behavioral Model Generation in Mixed-Signal System SimulationElectronics10.3390/electronics1009108810:9(1088)Online publication date: 4-May-2021
https://doi.org/10.3390/electronics10091088
Zivkovic CGrimm COlbrich MScharf OBarke E(2019)Hierarchical Verification of AMS Systems With Affine Arithmetic Decision DiagramsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.286423838:10(1785-1798)Online publication date: Oct-2019
https://doi.org/10.1109/TCAD.2018.2864238
Song YJung JShin Y(2017)Redundant Via insertion in SADP process with cut merging and optimization2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2017.8203478(1-6)Online publication date: Oct-2017
https://doi.org/10.1109/VLSI-SoC.2017.8203478
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Index Terms

An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Modeling methodologies

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Published In

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

April 2005

518 pages

ISBN:1595930574

DOI:10.1145/1057661

General Chair:
John Lach
University of Virginia
,
Program Chairs:
Gang Qu
University of Maryland, College Park
,
Yehea Ismail
Northwestern University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 17 April 2005

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GLSVLSI05: Great Lakes Symposium on VLSI 2005

April 17 - 19, 2005

Illinois, Chicago, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Song LLou YLin CLiu CHuang JJou JLee MLo Y(2021)Efficient Circuit Structure Analysis for Automatic Behavioral Model Generation in Mixed-Signal System SimulationElectronics10.3390/electronics1009108810:9(1088)Online publication date: 4-May-2021
https://doi.org/10.3390/electronics10091088
Zivkovic CGrimm COlbrich MScharf OBarke E(2019)Hierarchical Verification of AMS Systems With Affine Arithmetic Decision DiagramsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.286423838:10(1785-1798)Online publication date: Oct-2019
https://doi.org/10.1109/TCAD.2018.2864238
Song YJung JShin Y(2017)Redundant Via insertion in SADP process with cut merging and optimization2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2017.8203478(1-6)Online publication date: Oct-2017
https://doi.org/10.1109/VLSI-SoC.2017.8203478
Song LWang CLiu CLin YLee MLo YKao S(2017)Non-regression approach for the behavioral model generator in mixed-signal system verification2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2017.8203462(1-5)Online publication date: Oct-2017
https://doi.org/10.1109/VLSI-SoC.2017.8203462
Lin CDu XJiang XWang D(2016)An efficient and effective performance estimation method for DSE2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)10.1109/VLSI-DAT.2016.7482568(1-4)Online publication date: Apr-2016
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Lin YLee MLo YKao S(2016)Automatic mixed-signal behavioral model generation environment2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)10.1109/VLSI-DAT.2016.7482549(1-4)Online publication date: Apr-2016
https://doi.org/10.1109/VLSI-DAT.2016.7482549
Chen JWang SLin CLiu CLin YLee MLuo YKao S(2015)Automatic behavioral model generator for mixed-signal circuits based on structure recognition and auto-calibration2015 International SoC Design Conference (ISOCC)10.1109/ISOCC.2015.7401683(3-4)Online publication date: Nov-2015
https://doi.org/10.1109/ISOCC.2015.7401683
Chin-Cheng Kuo Chien-Nan Jimmy Liu (2005)Accurate behavioral modeling approach for PLL designs with supply noise effectsBMAS 2005. Proceedings of the 2005 IEEE International Behavioral Modeling and Simulation Workshop, 2005.10.1109/BMAS.2005.1518186(48-53)Online publication date: 2005
https://doi.org/10.1109/BMAS.2005.1518186

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