Article

The G⁴-FET: a universal and programmable logic gate

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P. GentilAuthors Info & Claims

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

Pages 349 - 352

https://doi.org/10.1145/1057661.1057745

Published: 17 April 2005 Publication History

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Abstract

The G⁴-FET, a four-gate transistor compatible with standard silicon-on-insulator (SOI) CMOS technology, provides unique opportunities as a logic device. Combining both JFET- and MOSFET-like actions within one transistor body, the G⁴-FET offers two side (lateral) junction-based gates, a top MOS gate, and a MOS back gate that is activated by SOI substrate biasing. The G⁴-FET's conduction characteristics are controlled by the combined interaction of these four gates. In this paper, the G⁴-FET is demonstrated as a logic device, resulting in a universal and programmable logic gate that can lead to the design of more efficient logic circuits. As an example, we present a new full adder design based on the G⁴-FET that is significantly more efficient than conventional designs.

References

[1]

B. J. Blalock, S. Cristoloveanu, B. M. Dufrene, F. Allibert, and M. M. Mojarradi, The Multiple-Gate MOS-JFET Transistor, Int. J. of High Speed Electronics and Systems, 12, 2 (2002), 511--520.

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[2]

S. Cristoloveanu, B. Blalock, F. Allibert, B.M. Dufrene, and M.M. Mojarradi, The Four-Gate Transistor, Proceedings of the 2002 European Solid-State Device Research Conf (Firenze, Italy, September 2002). 2002, 323--326.

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[3]

B. Dufrene, K. Akarvardar, S. Cristoloveanu, B. J. Blalock, P. Gentil, E. Kolawa, M. M. Mojarradi, Investigation of the Four Gate Action in G4-FETs, IEEE Trans. on Electron Devices, 51, 11 (Nov. 2004), 1931--1935.

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Cited By

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Sadia MPaul PHasan M(2023)Compact Analog Chaotic Map Designs Using SOI Four-Gate TransistorsIEEE Access10.1109/ACCESS.2023.329013311(64782-64795)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3290133
Sakib Hasan MShamim Ara Shawkat MAmer SKamrul Islam SMcFarlane NS. Rose G(2019)Modeling Emerging Semiconductor Devices for Circuit SimulationModeling and Simulation in Engineering [Working Title]10.5772/intechopen.85873Online publication date: 28-May-2019
https://doi.org/10.5772/intechopen.85873
Hasan MShamsir SShawkat MGarcia FIslam SRose G(2019) Macromodel of G 4 FET Enabling Fast and Reliable SPICE Simulation for Innovative Circuit Applications International Journal of High Speed Electronics and Systems10.1142/S012915641840015327:03n04(1840015)Online publication date: 2-May-2019
https://doi.org/10.1142/S0129156418400153
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Index Terms

The G⁴-FET: a universal and programmable logic gate
1. Hardware
  1. Integrated circuits
    1. Logic circuits
      1. Combinational circuits

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Published In

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

April 2005

518 pages

ISBN:1595930574

DOI:10.1145/1057661

General Chair:
John Lach
University of Virginia
,
Program Chairs:
Gang Qu
University of Maryland, College Park
,
Yehea Ismail
Northwestern University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 17 April 2005

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GLSVLSI05: Great Lakes Symposium on VLSI 2005

April 17 - 19, 2005

Illinois, Chicago, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Sadia MPaul PHasan M(2023)Compact Analog Chaotic Map Designs Using SOI Four-Gate TransistorsIEEE Access10.1109/ACCESS.2023.329013311(64782-64795)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3290133
Sakib Hasan MShamim Ara Shawkat MAmer SKamrul Islam SMcFarlane NS. Rose G(2019)Modeling Emerging Semiconductor Devices for Circuit SimulationModeling and Simulation in Engineering [Working Title]10.5772/intechopen.85873Online publication date: 28-May-2019
https://doi.org/10.5772/intechopen.85873
Hasan MShamsir SShawkat MGarcia FIslam SRose G(2019) Macromodel of G 4 FET Enabling Fast and Reliable SPICE Simulation for Innovative Circuit Applications International Journal of High Speed Electronics and Systems10.1142/S012915641840015327:03n04(1840015)Online publication date: 2-May-2019
https://doi.org/10.1142/S0129156418400153
Peled AHu XAmrani OFriedman JRosenwaks Y(2019)An SRAM Based on the MSET DeviceIEEE Transactions on Electron Devices10.1109/TED.2019.289231966:3(1262-1267)Online publication date: Mar-2019
https://doi.org/10.1109/TED.2019.2892319
Hasan MMahbub IIslam SRose G(2018) A MOS-JFET Macromodel of SOI Four-Gate Transistors (G 4 FET) to Aid Innovative Circuit Design 2018 IEEE 13th Dallas Circuits and Systems Conference (DCAS)10.1109/DCAS.2018.8620184(1-4)Online publication date: Nov-2018
https://doi.org/10.1109/DCAS.2018.8620184
Hasan MIslam S(2018) DC modelling of SOI four‐gate transistor (G 4 FET) for implementation in circuit simulator using multivariate regression polynomial IET Circuits, Devices & Systems10.1049/iet-cds.2018.005913:1(12-20)Online publication date: 26-Jun-2018
https://doi.org/10.1049/iet-cds.2018.0059
Hasan MRahman TIslam SBlalock B(2017)Numerical modeling and implementation in circuit simulator of SOI four-gate transistor (G4FET) using multidimensional Lagrange and Bernstein polynomialMicroelectronics Journal10.1016/j.mejo.2017.05.01165:C(84-93)Online publication date: 1-Jul-2017
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Friedman JGodkin AHenning AVaknin YRosenwaks YSahakian A(2016)Threshold Logic With Electrostatically Formed NanowiresIEEE Transactions on Electron Devices10.1109/TED.2015.251281863:3(1388-1391)Online publication date: Mar-2016
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Das AJahangir IHasan M(2014)Optimization of sum of product expressions in a novel quaternary algebra2014 International Conference on Informatics, Electronics & Vision (ICIEV)10.1109/ICIEV.2014.6850793(1-6)Online publication date: May-2014
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Aghababa HEbrahimi BSaremi MMoalemi VForouzandeh B(2012)G4-FET modeling for circuit simulation by adaptive neuro-fuzzy training systemsIEICE Electronics Express10.1587/elex.9.8819:10(881-887)Online publication date: 2012
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Recommendations

Subthreshold slope modulation in G4-FET transistor

Design of a mask-programmable memory/multiplier array using G4-FET technology

Performance estimation of sub-30 nm junctionless tunnel FET (JLTFET)

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Subthreshold slope modulation in G⁴-FET transistor