Article

Dual-transition glitch filtering in probabilistic waveform power estimation

Authors:

Fei Hu,

Vishwani D. AgrawalAuthors Info & Claims

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

Pages 357 - 360

https://doi.org/10.1145/1057661.1057747

Published: 17 April 2005 Publication History

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Abstract

Existing gate-level probabilistic approaches to power estimation fail to accurately model the glitch filtering by inertial delays. This effect has an impact on the power dissipation of a circuit and should not be neglected, especially for dynamic power estimation of circuits with dynamic power optimization. We propose a new glitch filtering analysis using the dual-transition probability that captures the states of a node at two different time instances. Experiments show that probabilistic simulation and the tagged probability simulation (TPS) techniques, when enhanced by the dual-transition analysis, provide more consistent power estimation. For circuits with a large component of glitch power, up to 29% improvement in the estimation accuracy is obtained.

References

[1]

Chandrakasan, A. P. and Brodersen, R. W. Low power digital CMOS design. Kluwer academic publishers, Boston, 1995.

Digital Library

Google Scholar

[2]

Cirit, M. A. Estimating dynamic power consumption of CMOS circuits. In Proc. ICCAD, 1987, 534--537.

Google Scholar

[3]

Ding, C.-S., Tsui,C.-Y., and Pedram, M. Gate-level power estimation using tagged probabilistic simulation. IEEE Trans. on CAD, 17, 11 (Nov. 1998), 1099--1107.

Digital Library

Google Scholar

[4]

Ercolani, S., Favalli, M., Damiani, M., Olivo, P., and Ricco, B. Estimate of signal probability in combinational logic networks. In Proc. of First European Test Conference, 1989, 132--138.

Crossref

Google Scholar

[5]

Najm, F. N., Burch, R., Yang, P., and Hajj, I. N. CREST - a current estimator for CMOS circuits. In Proc. ICCAD, Nov. 1988, 204--207.

Crossref

Google Scholar

[6]

Najm, F. N., Burch, R., Yang, P., and Hajj, I. N. Probabilistic simulation for reliability analysis of CMOS VLSI circuits. IEEE Trans. on CAD, 9, 4 (Apr. 1990), 439--450.

Digital Library

Google Scholar

[7]

Najm, F. N. Transition density: a new measure of activity in digital circuits. IEEE Trans. on CAD, 12, 2 (Feb. 1993), 310--323.

Digital Library

Google Scholar

[8]

Marculescu, R., Marculescu, D., and Pedram, M. Logic level power estimation considering spatiotemporal correlations. In Proc. ICCAD, Nov. 1994, 294--299.

Digital Library

Google Scholar

[9]

Marculescu, R., Marculescu, D., and Pedram, M. Efficient power estimation for highly correlated input streams. In Proc. 32nd DAC, June 1995, 628--634.

Digital Library

Google Scholar

[10]

Schneider, P. and Schlichtmann, U. Decomposition of Boolean functions for low power based on a new power estimation technique. In Proc. International Workshop on Low Power Design, Apr. 1994, 123--128.

Digital Library

Google Scholar

[11]

Theodoridis, G., Theoharis, S., Soudris, D., Stouraitis, T., and Goutis, C. An efficient probabilistic method for logic circuits using real delay gate model. In Proc. ISCAS, vol. 1, Jun. 1999, 286--289.

Crossref

Google Scholar

[12]

Tsui, C.-Y., Pedram, M., and Despain, A. M. Efficient estimation of dynamic power consumption under a real delay model. In Proc. ICCAD, Nov. 1993, 224--228.

Digital Library

Google Scholar

Cited By

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Ren LSun SDeo MJaffari JAnmula PBoyle PDrewniak JBeetner D(2016)A Vectorless Approach for Predicting Switching Activity in a Digital CircuitIEEE Transactions on Electromagnetic Compatibility10.1109/TEMC.2016.252164658:3(828-835)Online publication date: Jun-2016
https://doi.org/10.1109/TEMC.2016.2521646
Anju PRamesh S(2012)Toggle rate estimation technique for FPGA circuits considering spatial correlation2012 Third International Conference on Computing, Communication and Networking Technologies (ICCCNT'12)10.1109/ICCCNT.2012.6395937(1-7)Online publication date: Jul-2012
https://doi.org/10.1109/ICCCNT.2012.6395937
Czajkowski TBrown S(2010)Decomposition-based vectorless toggle rate computation for FPGA circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.206125029:11(1723-1735)Online publication date: 1-Nov-2010
https://dl.acm.org/doi/10.1109/TCAD.2010.2061250
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Index Terms

Dual-transition glitch filtering in probabilistic waveform power estimation
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Modeling methodologies

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Published In

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

April 2005

518 pages

ISBN:1595930574

DOI:10.1145/1057661

General Chair:
John Lach
University of Virginia
,
Program Chairs:
Gang Qu
University of Maryland, College Park
,
Yehea Ismail
Northwestern University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 17 April 2005

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GLSVLSI05: Great Lakes Symposium on VLSI 2005

April 17 - 19, 2005

Illinois, Chicago, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Ren LSun SDeo MJaffari JAnmula PBoyle PDrewniak JBeetner D(2016)A Vectorless Approach for Predicting Switching Activity in a Digital CircuitIEEE Transactions on Electromagnetic Compatibility10.1109/TEMC.2016.252164658:3(828-835)Online publication date: Jun-2016
https://doi.org/10.1109/TEMC.2016.2521646
Anju PRamesh S(2012)Toggle rate estimation technique for FPGA circuits considering spatial correlation2012 Third International Conference on Computing, Communication and Networking Technologies (ICCCNT'12)10.1109/ICCCNT.2012.6395937(1-7)Online publication date: Jul-2012
https://doi.org/10.1109/ICCCNT.2012.6395937
Czajkowski TBrown S(2010)Decomposition-based vectorless toggle rate computation for FPGA circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.206125029:11(1723-1735)Online publication date: 1-Nov-2010
https://dl.acm.org/doi/10.1109/TCAD.2010.2061250
Czajkowski TBrown S(2008)Fast toggle rate computation for FPGA circuits2008 International Conference on Field Programmable Logic and Applications10.1109/FPL.2008.4629909(65-70)Online publication date: Sep-2008
https://doi.org/10.1109/FPL.2008.4629909
Oskuii SKjeldsberg PAas EZhou HMacii EYan ZMassoud Y(2007)Probabilistic gate-level power estimation using a novel waveform set methodProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228799(37-42)Online publication date: 11-Mar-2007
https://dl.acm.org/doi/10.1145/1228784.1228799
Oskuii SKjeldsberg PGustafsson O(2007)Power optimized partial product reduction interconnect ordering in parallel multipliersNorchip 200710.1109/NORCHP.2007.4481034(1-6)Online publication date: Nov-2007
https://doi.org/10.1109/NORCHP.2007.4481034
Hu FAgrawal V(2005)Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate AnalysisProceedings of the 2005 International Conference on Computer Design10.1109/ICCD.2005.49(366-372)Online publication date: 2-Oct-2005
https://dl.acm.org/doi/10.1109/ICCD.2005.49

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Recommendations

Modeling of Short Circuit Power Consumption Using Timing-Only Logic Cell Macromodels

Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis

Fast power loss calculation for digital static CMOS circuits

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