Article

Low-overhead state-retaining elements for low-leakage MTCMOS design

Authors:

Pietro Babighian,

Luca Benini,

Alberto Macii,

Enrico MaciiAuthors Info & Claims

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

Pages 367 - 370

https://doi.org/10.1145/1057661.1057749

Published: 17 April 2005 Publication History

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Abstract

Multi-threshold CMOS (MTCMOS) has shown to be a very effective technique for reducing sub-threshold leakage currents in DSM CMOS designs. Application of the MTC-MOS paradigm to sequential circuits requires the availability of data-retaining elements for storing circuit state during stand-by mode. In this paper we propose two novel circuit schemes for sequential elements featuring low leakage currents in stand-by mode and high-speed/low-dynamic power in active mode. We present post-layout simulation results obtained after parasitic extraction for delay and power of circuits built in 130nm CMOS technology. Our experiments demonstrate several advantages of the proposed schemes over the best previously published solutions.

References

[1]

J. Kao, S. Narendra, A. Chandrakasan, "MTCMOS Hierarchical Sizing based on Mutual Exclusive Discharge Patterns," DAC-35: ACM/IEEE Design Automation Conference, pp. 495--500 San Francisco, CA, June 1998.

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[2]

S. Mutoh, S. Shigematsu, Y. Matsuya, H. Fukuda, T. Kaneko, A 1-V Multithreshold-Voltage CMOS Digital Signal Processor for Mobile Phone Applications", IEEE Journal of Solid-State Circuits, vol.31, no.11, pp. 1795--1802, 1996.

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S.V. Kovosonocky, Low-Power Circuits and Technology for Wireless Digital Systems", IBM Journal Research and & Development, vol.47, no. 2/3, pp. 1795--1802, March 2003.

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[4]

P. Babighian, L. Benini, E. Macii, Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating", DATE-04: IEEE 2004 Design Automation and Test in Europe, pp. 720--721, Paris, France, February 2004.

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[5]

P. Babighian, L. Benini, A. Macii, E. Macii, Post-Layout Leakage Power Minimization Based on Distributed Sleep Transistor Insertion", ISLPED-04: ACM/IEEE International Symposium on Low Power Electronics and Design, pp. 138--143, Newport Beach, CA, August 2004.

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Index Terms

Low-overhead state-retaining elements for low-leakage MTCMOS design
1. Hardware
  1. Very large scale integration design

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Published In

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

April 2005

518 pages

ISBN:1595930574

DOI:10.1145/1057661

General Chair:
John Lach
University of Virginia
,
Program Chairs:
Gang Qu
University of Maryland, College Park
,
Yehea Ismail
Northwestern University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 17 April 2005

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April 17 - 19, 2005

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Abstract

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Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs

A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations

A forward body-biased low-leakage SRAM cache: device and architecture considerations

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