Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMs
Pages 377 - 380
Abstract
Application-Specific Block-Enabled (ASBE) SRAMs represent a viable solution for reducing energy consumption in embedded memories. The basic idea behind ASBE architectures is that of partitioning the memory array into a number of non-uniformly sized blocks, such that memory access cost is reduced. The number and sizes of the partitions yielding a minimum power implementation of the SRAM macro is determined by the partitioning algorithm based on the memory access profile obtained as a result of the application (or application mix) executed by the processor. Given the complexity of the design space we are dealing with, there are several degrees of freedom that the partitioning engine may exploit to come up with the most energy-efficient memory architecture. In this paper, we investigate how the quality of the partitioned memory depends on the architectural parameters that define the memory structure (e.g., min and max number of lines per partition, min and max number of words per line, granularity of the partitions); such parameters, in turn, are constrained by the technology and process of choice. We believe that the results presented in this work will provide very useful guidelines for a succesfull adoption of the ASBE approach in practice, as this design paradigm is gaining a lot of attention for the new generations of embedded systems.
References
[1]
L. Benini et al. "Block Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning", Design Automation and Test in Europe, pp. 698--699 Vol.1, Paris, Feb 2004.
[2]
L. Benini, A. Macii, M. Poncino, "Memory Design Techniques for Low-Energy Embedded Systems", Kluwer Academic Publishers, Dordrecht, Netherlands, 2002.
[3]
S. L. Coumeri, D. E. Thomas, "An Environment for Exploring Low-Power Memory Configurations in System-Level Design", ICCD-99: IEEE International Conference on Computer Design, pp. 348--353, Austin, TX, October 1999.
[4]
N. Kawabe, K. Usami, "Low-Power Technique for On-Chip Memory using Biased Partitioning and Access Concentration", CICC-00: IEEE Custom Integrated Circuits Conference, pp. 275--278, San Diego, CA, May 2002.
[5]
L. Benini et al. "Layout-Driven Memory Synthesis for Embedded Systems-on-Chip", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 2, pp. 96--105, April~2002.
[6]
A. Karandikar et al. "Low Power SRAM Design using Hierarchical Divided Bit-Line Approach", ICCD-98: IEEE International Conference on Computer Design, pp. 82--88, Austin, TX, October 1998.
[7]
M. Yoshimoto et al. "A Divided Word-Line Structure in the Static RAM and Its Application to a 64K Full CMOS RAM", IEEE Journal of Solid-State Circuits, Vol. 18, No. 5, pp. 479--485, October 1983.
[8]
C. Lee et al. "MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems", 30th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 330--335, Research Triangle Park, NC, 1997.
[9]
ARM Ltd., RealView ARMulator ISS, http://www.arm.com/devtools/iss.
[10]
A. Macii et al. "Design and Implementation of a Memory Generator for Application-Specific Block-Enabled SRAMs", Submitted to Design Automation Conference (DAC) 2005.
Index Terms
- Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMs
Recommendations
A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies
Many new memory technologies are available for building future energy-efficient memory hierarchies. It is necessary to have a framework that can quickly find the optimal memory technology at each hierarchy level. In this work, we first build a circuit-...
Efficient Utilization of Scratch-Pad Memory in Embedded Processor Applications
EDTC '97: Proceedings of the 1997 European conference on Design and TestEfficient utilization of on-chip memory space is extremely important in modern embedded system applications based on microprocessor cores. In addition to a data cache that interfaces with slower off-chip memory, a fast on-chip SRAM, called Scratch-Pad ...
Design and implementation of a memory generator for low-energy application-specific block-enabled SRAMs
PATMOS'05: Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and SimulationMemory partitioning has proved to be a promising solution to reduce energy consumption in complex SoCs. Memory partitioning comes in different flavors, depending on the specific domain of usage and design constraints to be met. In this paper, we ...
Comments
Information & Contributors
Information
Published In
April 2005
518 pages
Copyright © 2005 ACM.
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]
Sponsors
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Published: 17 April 2005
Check for updates
Author Tags
Qualifiers
- Article
Conference
Acceptance Rates
Overall Acceptance Rate 312 of 1,156 submissions, 27%
Upcoming Conference
GLSVLSI '25
- Sponsor:
- sigda
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 129Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0
Reflects downloads up to 07 Mar 2025
Other Metrics
Citations
View Options
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in