Ali Bastani
ABSTRACT
This paper reviews the use of skewed monotonic static CMOS logic gates in scaled technologies where gate leakage currents become significant. High-level tradeoffs and synthesis approaches are discussed, and some experiments are constructed to evaluate the gate-level performance tradeoffs in a hypothetical standard 65nm CMOS technology. At the gate level, significant improvements in static power consumption are possible without reduction in evaluation delays, but the tradeoffs vary as the conditions and the amount of skewing are changed. NAND forms are still preferred as the gate leakage grows.
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Index Terms
- Characterization of monotonic static CMOS gates in a 65nm technology
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