Article

Characterization of monotonic static CMOS gates in a 65nm technology

Authors:

Ali Bastani,

Charles A. ZukowskiAuthors Info & Claims

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

Pages 408 - 411

https://doi.org/10.1145/1057661.1057758

Published: 17 April 2005 Publication History

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Abstract

This paper reviews the use of skewed monotonic static CMOS logic gates in scaled technologies where gate leakage currents become significant. High-level tradeoffs and synthesis approaches are discussed, and some experiments are constructed to evaluate the gate-level performance tradeoffs in a hypothetical standard 65nm CMOS technology. At the gate level, significant improvements in static power consumption are possible without reduction in evaluation delays, but the tradeoffs vary as the conditions and the amount of skewing are changed. NAND forms are still preferred as the gate leakage grows.

References

[1]

http://www-devices.eecs.berkeley.edu/

Google Scholar

[2]

http://www.aimspice.com/

Google Scholar

[3]

http://www.itrs.net, 2004 International Technology Roadmap for Semiconductors.

Google Scholar

[4]

C. Kim, et. al., "Energy-efficient skewed static logic with dual Vt: design and synthesis," IEEE Trans. VLSI Systems, vol. 11, no. 1, Feb. 2003, pp. 64--70.

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Google Scholar

[5]

T. Thorp, et. al., "Design and Synthesis of Dynamic Circuits," IEEE Trans. VLSI Systems, vol. 11, no. 1, Feb. 2003, pp. 141--149.

Digital Library

Google Scholar

[6]

P. Chin, et. al., "Characterization of Logic Circuit Techniques for High Leakage CMOS Technologies," in Proc. of ACM GLS-VLSI, 2004, pp. 230--235.

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Kalyani Garimella LRaga Sudha Garimella S(2019)Novel 3D Monotonic Characterization of Standard Cell Liberty File Attributes w.r.t ASIC Tool Flow2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2019.8884936(227-230)Online publication date: Aug-2019
https://doi.org/10.1109/MWSCAS.2019.8884936
Garimella LGarimella S(2018)Novel 3D Monotonic Characterization of Standard Cell Liberty File Attributes w.r.t ASIC Tool Flow2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2018.8624015(771-774)Online publication date: Aug-2018
https://doi.org/10.1109/MWSCAS.2018.8624015
Beg A(2015)A web-based method for building and simulating standard cell circuits-A classroom applicationComputer Applications in Engineering Education10.1002/cae.2160023:2(304-313)Online publication date: 1-Mar-2015
https://dl.acm.org/doi/10.1002/cae.21600
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Index Terms

Characterization of monotonic static CMOS gates in a 65nm technology
1. Hardware
  1. Very large scale integration design

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Published In

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

April 2005

518 pages

ISBN:1595930574

DOI:10.1145/1057661

General Chair:
John Lach
University of Virginia
,
Program Chairs:
Gang Qu
University of Maryland, College Park
,
Yehea Ismail
Northwestern University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 17 April 2005

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GLSVLSI05: Great Lakes Symposium on VLSI 2005

April 17 - 19, 2005

Illinois, Chicago, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Kalyani Garimella LRaga Sudha Garimella S(2019)Novel 3D Monotonic Characterization of Standard Cell Liberty File Attributes w.r.t ASIC Tool Flow2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2019.8884936(227-230)Online publication date: Aug-2019
https://doi.org/10.1109/MWSCAS.2019.8884936
Garimella LGarimella S(2018)Novel 3D Monotonic Characterization of Standard Cell Liberty File Attributes w.r.t ASIC Tool Flow2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2018.8624015(771-774)Online publication date: Aug-2018
https://doi.org/10.1109/MWSCAS.2018.8624015
Beg A(2015)A web-based method for building and simulating standard cell circuits-A classroom applicationComputer Applications in Engineering Education10.1002/cae.2160023:2(304-313)Online publication date: 1-Mar-2015
https://dl.acm.org/doi/10.1002/cae.21600
Beg A(2013)Automatic generation of characterization circuits - An application in academia2013 IEEE Frontiers in Education Conference (FIE)10.1109/FIE.2013.6684909(661-664)Online publication date: Oct-2013
https://doi.org/10.1109/FIE.2013.6684909
Beg AElchouemi ABeg R(2013)A collaborative platform for facilitating standard cell characterizationProceedings of the 2013 IEEE 17th International Conference on Computer Supported Cooperative Work in Design (CSCWD)10.1109/CSCWD.2013.6580963(202-206)Online publication date: Jun-2013
https://doi.org/10.1109/CSCWD.2013.6580963
Irez KHu JZukowski CBahar RLombardi FAtienza DBrunvand E(2010)Characteristics of MS-CMOS logic in sub-32nm technologiesProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785572(393-396)Online publication date: 16-May-2010
https://dl.acm.org/doi/10.1145/1785481.1785572
Bastani AZukowski CQu GIsmail YNarayanan VZhou H(2006)Monotonic static CMOS tradeoffs in sub-100nm technologiesProceedings of the 16th ACM Great Lakes symposium on VLSI10.1145/1127908.1127973(278-283)Online publication date: 30-Apr-2006
https://dl.acm.org/doi/10.1145/1127908.1127973
Bastani AZukowski C(2006)A Low-Leakage High-Speed Monotonic Static CMOS 64b Adder in a Dual Gate Oxide 65-nm CMOS TechnologyProceedings of the 7th International Symposium on Quality Electronic Design10.1109/ISQED.2006.12(312-317)Online publication date: 27-Mar-2006
https://dl.acm.org/doi/10.1109/ISQED.2006.12

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Design of superbuffers in sub-100nm CMOS technologies with significant gate leakage

Monotonic static CMOS tradeoffs in sub-100nm technologies

Body-bias compensation technique for SubThreshold CMOS static logic gates

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